Intel 253668-032US User Manual
16-14 Vol. 3
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
16.4
LAST BRANCH, INTERRUPT, AND EXCEPTION
RECORDING OVERVIEW
P6 family processors introduced the ability to set breakpoints on taken branches,
interrupts, and exceptions, and to single-step from one branch to the next. This
capability has been modified and extended in the Pentium 4, Intel Xeon, Pentium M,
Intel
interrupts, and exceptions, and to single-step from one branch to the next. This
capability has been modified and extended in the Pentium 4, Intel Xeon, Pentium M,
Intel
®
Core™ Solo, Intel
®
Core™ Duo, Intel
®
Core™2 Duo, Intel
®
Core™ i7 and
Intel
®
Atom™ processors to allow logging of branch trace messages in a branch trace
store (BTS) buffer in memory.
See the following sections for processor specific implementation of last branch, inter-
rupt and exception recording:
See the following sections for processor specific implementation of last branch, inter-
rupt and exception recording:
The following subsections of Section 16.4 describe common features of profiling
branches. These features are generally enabled using the IA32_DEBUGCTL MSR
(older processor may have implemented a subset or model-specific features, see
definitions of MSR_DEBUGCTLA, MSR_DEBUGCTLB, MSR_DEBUGCTL).
branches. These features are generally enabled using the IA32_DEBUGCTL MSR
(older processor may have implemented a subset or model-specific features, see
definitions of MSR_DEBUGCTLA, MSR_DEBUGCTLB, MSR_DEBUGCTL).
16.4.1 IA32_DEBUGCTL
MSR
The IA32_DEBUGCTL MSR provides bit field controls to enable debug trace inter-
rupts, debug trace stores, trace messages enable, single stepping on branches, last
branch record recording, and to control freezing of LBR stack or performance
counters on a PMI request. IA32_DEBUGCTL MSR is located at register address
01D9H.
See Figure 16-3 for the MSR layout and the bullets below for a description of the
flags:
rupts, debug trace stores, trace messages enable, single stepping on branches, last
branch record recording, and to control freezing of LBR stack or performance
counters on a PMI request. IA32_DEBUGCTL MSR is located at register address
01D9H.
See Figure 16-3 for the MSR layout and the bullets below for a description of the
flags:
•
LBR (last branch/interrupt/exception) flag (bit 0) — When set, the
processor records a running trace of the most recent branches, interrupts, and/or
exceptions taken by the processor (prior to a debug exception being generated)
processor records a running trace of the most recent branches, interrupts, and/or
exceptions taken by the processor (prior to a debug exception being generated)