Intel 253668-032US User Manual
16-12 Vol. 3
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
16.3.1.2 Data Memory and I/O Breakpoint Exception Conditions
Data memory and I/O breakpoints are reported when the processor attempts to
access a memory or I/O address specified in a breakpoint-address register (DB0
through DR3) that has been set up to detect data or I/O accesses (R/W flag is set to
1, 2, or 3). The processor generates the exception after it executes the instruction
that made the access, so these breakpoint condition causes a trap-class exception to
be generated.
Because data breakpoints are traps, the original data is overwritten before the trap
exception is generated. If a debugger needs to save the contents of a write break-
point location, it should save the original contents before setting the breakpoint. The
handler can report the saved value after the breakpoint is triggered. The address in
the debug registers can be used to locate the new value stored by the instruction that
triggered the breakpoint.
Intel486 and later processors ignore the GE and LE flags in DR7. In Intel386 proces-
sors, exact data breakpoint matching does not occur unless it is enabled by setting
the LE and/or the GE flags.
P6 family processors are unable to report data breakpoints exactly for the REP MOVS
and REP STOS instructions until the completion of the iteration after the iteration in
which the breakpoint occurred.
For repeated INS and OUTS instructions that generate an I/O-breakpoint debug
exception, the processor generates the exception after the completion of the first
iteration. Repeated INS and OUTS instructions generate a memory-breakpoint debug
exception after the iteration in which the memory address breakpoint location is
accessed.
access a memory or I/O address specified in a breakpoint-address register (DB0
through DR3) that has been set up to detect data or I/O accesses (R/W flag is set to
1, 2, or 3). The processor generates the exception after it executes the instruction
that made the access, so these breakpoint condition causes a trap-class exception to
be generated.
Because data breakpoints are traps, the original data is overwritten before the trap
exception is generated. If a debugger needs to save the contents of a write break-
point location, it should save the original contents before setting the breakpoint. The
handler can report the saved value after the breakpoint is triggered. The address in
the debug registers can be used to locate the new value stored by the instruction that
triggered the breakpoint.
Intel486 and later processors ignore the GE and LE flags in DR7. In Intel386 proces-
sors, exact data breakpoint matching does not occur unless it is enabled by setting
the LE and/or the GE flags.
P6 family processors are unable to report data breakpoints exactly for the REP MOVS
and REP STOS instructions until the completion of the iteration after the iteration in
which the breakpoint occurred.
For repeated INS and OUTS instructions that generate an I/O-breakpoint debug
exception, the processor generates the exception after the completion of the first
iteration. Repeated INS and OUTS instructions generate a memory-breakpoint debug
exception after the iteration in which the memory address breakpoint location is
accessed.
16.3.1.3 General-Detect Exception Condition
When the GD flag in DR7 is set, the general-detect debug exception occurs when a
program attempts to access any of the debug registers (DR0 through DR7) at the
same time they are being used by another application, such as an emulator or
debugger. This protection feature guarantees full control over the debug registers
when required. The debug exception handler can detect this condition by checking
the state of the BD flag in the DR6 register. The processor generates the exception
before it executes the MOV instruction that accesses a debug register, which causes
a fault-class exception to be generated.
program attempts to access any of the debug registers (DR0 through DR7) at the
same time they are being used by another application, such as an emulator or
debugger. This protection feature guarantees full control over the debug registers
when required. The debug exception handler can detect this condition by checking
the state of the BD flag in the DR6 register. The processor generates the exception
before it executes the MOV instruction that accesses a debug register, which causes
a fault-class exception to be generated.
16.3.1.4 Single-Step Exception Condition
The processor generates a single-step debug exception if (while an instruction is
being executed) it detects that the TF flag in the EFLAGS register is set. The excep-
tion is a trap-class exception, because the exception is generated after the instruc-
tion is executed. The processor will not generate this exception after the instruction
that sets the TF flag. For example, if the POPF instruction is used to set the TF flag, a
being executed) it detects that the TF flag in the EFLAGS register is set. The excep-
tion is a trap-class exception, because the exception is generated after the instruc-
tion is executed. The processor will not generate this exception after the instruction
that sets the TF flag. For example, if the POPF instruction is used to set the TF flag, a