Intel 253668-032US User Manual
6-6 Vol. 3
INTERRUPT AND EXCEPTION HANDLING
6.4.2 Software-Generated
Exceptions
The INTO, INT 3, and BOUND instructions permit exceptions to be generated in soft-
ware. These instructions allow checks for exception conditions to be performed at
points in the instruction stream. For example, INT 3 causes a breakpoint exception to
be generated.
The INT n instruction can be used to emulate exceptions in software; but there is a
limitation. If INT n provides a vector for one of the architecturally-defined excep-
tions, the processor generates an interrupt to the correct vector (to access the
exception handler) but does not push an error code on the stack. This is true even if
the associated hardware-generated exception normally produces an error code. The
exception handler will still attempt to pop an error code from the stack while handling
the exception. Because no error code was pushed, the handler will pop off and
discard the EIP instead (in place of the missing error code). This sends the return to
the wrong location.
ware. These instructions allow checks for exception conditions to be performed at
points in the instruction stream. For example, INT 3 causes a breakpoint exception to
be generated.
The INT n instruction can be used to emulate exceptions in software; but there is a
limitation. If INT n provides a vector for one of the architecturally-defined excep-
tions, the processor generates an interrupt to the correct vector (to access the
exception handler) but does not push an error code on the stack. This is true even if
the associated hardware-generated exception normally produces an error code. The
exception handler will still attempt to pop an error code from the stack while handling
the exception. Because no error code was pushed, the handler will pop off and
discard the EIP instead (in place of the missing error code). This sends the return to
the wrong location.
6.4.3 Machine-Check
Exceptions
The P6 family and Pentium processors provide both internal and external machine-
check mechanisms for checking the operation of the internal chip hardware and bus
transactions. These mechanisms are implementation dependent. When a machine-
check error is detected, the processor signals a machine-check exception (vector 18)
and returns an error code.
See Chapter 6, “Interrupt 18—Machine-Check Exception (#MC)” and Chapter 15,
“Machine-Check Architecture,” for more information about the machine-check
mechanism.
check mechanisms for checking the operation of the internal chip hardware and bus
transactions. These mechanisms are implementation dependent. When a machine-
check error is detected, the processor signals a machine-check exception (vector 18)
and returns an error code.
See Chapter 6, “Interrupt 18—Machine-Check Exception (#MC)” and Chapter 15,
“Machine-Check Architecture,” for more information about the machine-check
mechanism.
6.5 EXCEPTION
CLASSIFICATIONS
Exceptions are classified as faults, traps, or aborts depending on the way they are
reported and whether the instruction that caused the exception can be restarted
without loss of program or task continuity.
reported and whether the instruction that caused the exception can be restarted
without loss of program or task continuity.
•
Faults — A fault is an exception that can generally be corrected and that, once
corrected, allows the program to be restarted with no loss of continuity. When a
fault is reported, the processor restores the machine state to the state prior to
the beginning of execution of the faulting instruction. The return address (saved
contents of the CS and EIP registers) for the fault handler points to the faulting
instruction, rather than to the instruction following the faulting instruction.
corrected, allows the program to be restarted with no loss of continuity. When a
fault is reported, the processor restores the machine state to the state prior to
the beginning of execution of the faulting instruction. The return address (saved
contents of the CS and EIP registers) for the fault handler points to the faulting
instruction, rather than to the instruction following the faulting instruction.
•
Traps — A trap is an exception that is reported immediately following the
execution of the trapping instruction. Traps allow execution of a program or task
to be continued without loss of program continuity. The return address for the
trap handler points to the instruction to be executed after the trapping
instruction.
execution of the trapping instruction. Traps allow execution of a program or task
to be continued without loss of program continuity. The return address for the
trap handler points to the instruction to be executed after the trapping
instruction.