Intel 253668-032US User Manual
6-4 Vol. 3
INTERRUPT AND EXCEPTION HANDLING
The processor’s local APIC is normally connected to a system-based I/O APIC. Here,
external interrupts received at the I/O APIC’s pins can be directed to the local APIC
through the system bus (Pentium 4, Intel Core Duo, Intel Core 2, Intel Atom, and
Intel Xeon processors) or the APIC serial bus (P6 family and Pentium processors).
The I/O APIC determines the vector number of the interrupt and sends this number
to the local APIC. When a system contains multiple processors, processors can also
send interrupts to one another by means of the system bus (Pentium 4, Intel Core
Duo, Intel Core 2, Intel Atom, and Intel Xeon processors) or the APIC serial bus (P6
family and Pentium processors).
The LINT[1:0] pins are not available on the Intel486 processor and earlier Pentium
processors that do not contain an on-chip local APIC. These processors have dedi-
cated NMI and INTR pins. With these processors, external interrupts are typically
generated by a system-based interrupt controller (8259A), with the interrupts being
signaled through the INTR pin.
Note that several other pins on the processor can cause a processor interrupt to
occur. However, these interrupts are not handled by the interrupt and exception
mechanism described in this chapter. These pins include the RESET#, FLUSH#,
STPCLK#, SMI#, R/S#, and INIT# pins. Whether they are included on a particular
processor is implementation dependent. Pin functions are described in the data
books for the individual processors. The SMI# pin is described in Chapter 26,
“System Management.”
external interrupts received at the I/O APIC’s pins can be directed to the local APIC
through the system bus (Pentium 4, Intel Core Duo, Intel Core 2, Intel Atom, and
Intel Xeon processors) or the APIC serial bus (P6 family and Pentium processors).
The I/O APIC determines the vector number of the interrupt and sends this number
to the local APIC. When a system contains multiple processors, processors can also
send interrupts to one another by means of the system bus (Pentium 4, Intel Core
Duo, Intel Core 2, Intel Atom, and Intel Xeon processors) or the APIC serial bus (P6
family and Pentium processors).
The LINT[1:0] pins are not available on the Intel486 processor and earlier Pentium
processors that do not contain an on-chip local APIC. These processors have dedi-
cated NMI and INTR pins. With these processors, external interrupts are typically
generated by a system-based interrupt controller (8259A), with the interrupts being
signaled through the INTR pin.
Note that several other pins on the processor can cause a processor interrupt to
occur. However, these interrupts are not handled by the interrupt and exception
mechanism described in this chapter. These pins include the RESET#, FLUSH#,
STPCLK#, SMI#, R/S#, and INIT# pins. Whether they are included on a particular
processor is implementation dependent. Pin functions are described in the data
books for the individual processors. The SMI# pin is described in Chapter 26,
“System Management.”
6.3.2
Maskable Hardware Interrupts
Any external interrupt that is delivered to the processor by means of the INTR pin or
through the local APIC is called a maskable hardware interrupt. Maskable hardware
interrupts that can be delivered through the INTR pin include all IA-32 architecture
through the local APIC is called a maskable hardware interrupt. Maskable hardware
interrupts that can be delivered through the INTR pin include all IA-32 architecture
18
#MC
Machine Check
Abort
No
Error codes (if any) and source
are model dependent.
4
19
#XM
SIMD Floating-Point
Exception
Fault
No
SSE/SSE2/SSE3 floating-point
instructions
5
20-31
—
Intel reserved. Do not use.
32-
255
—
User Defined (Non-
reserved) Interrupts
Interrupt
External interrupt or INT n
instruction.
NOTES:
1. The UD2 instruction was introduced in the Pentium Pro processor.
2. Processors after the Intel386 processor do not generate this exception.
3. This exception was introduced in the Intel486 processor.
4. This exception was introduced in the Pentium processor and enhanced in the P6 family proces-
2. Processors after the Intel386 processor do not generate this exception.
3. This exception was introduced in the Intel486 processor.
4. This exception was introduced in the Pentium processor and enhanced in the P6 family proces-
sors.
5. This exception was introduced in the Pentium III processor.
Table 6-1. Protected-Mode Exceptions and Interrupts (Contd.)