Manual Do Utilizadoríndice analítico8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’s Manual4CONTENTS6CHAPTER 1 GUIDE TO THIS MANUAL241.1 MANUAL CONTENTS241.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY261.3 RELATED DOCUMENTS281.4 ELECTRONIC SUPPORT SYSTEMS311.4.1 FaxBack Service311.4.2 Bulletin Board System (BBS)321.4.2.1 How to Find MCS ® 96 Microcontroller Files on the BBS331.4.2.2 How to Find ApBUILDER Software and Hypertext Documents on the BBS331.4.3 CompuServe Forums331.4.4 World Wide Web341.5 TECHNICAL SUPPORT341.6 PRODUCT LITERATURE34CHAPTER 2 ARCHITECTURAL OVERVIEW382.1 TYPICAL APPLICATIONS382.2 MICROCONTROLLER FEATURES382.3 FUNCTIONAL OVERVIEW392.3.1 CPU Control412.3.2 Register File412.3.3 Register Arithmetic-logic Unit (RALU)412.3.3.1 Code Execution422.3.3.2 Instruction Format422.3.4 Memory Interface Unit432.3.5 Interrupt Service432.4 INTERNAL TIMING442.5 INTERNAL PERIPHERALS452.5.1 I/O Ports462.5.2 Serial I/O (SIO) Port462.5.3 Event Processor Array (EPA) and Timer/Counters472.5.4 Pulse-width Modulator (PWM)472.5.5 Frequency Generator472.5.6 Waveform Generator472.5.7 Analog-to-digital Converter482.5.8 Watchdog Timer482.6 SPECIAL OPERATING MODES482.6.1 Reducing Power Consumption482.6.2 Testing the Printed Circuit Board482.6.3 Programming the Nonvolatile Memory49CHAPTER 3 PROGRAMMING CONSIDERATIONS523.1 OVERVIEW OF THE INSTRUCTION SET523.1.1 BIT Operands533.1.2 BYTE Operands533.1.3 SHORT-INTEGER Operands533.1.4 WORD Operands533.1.5 INTEGER Operands543.1.6 DOUBLE-WORD Operands543.1.7 LONG-INTEGER Operands553.1.8 Converting Operands553.1.9 Conditional Jumps553.1.10 Floating Point Operations553.2 ADDRESSING MODES563.2.1 Direct Addressing573.2.2 Immediate Addressing573.2.3 Indirect Addressing573.2.3.1 Indirect Addressing with Autoincrement583.2.3.2 Indirect Addressing with the Stack Pointer583.2.4 Indexed Addressing583.2.4.1 Short-indexed Addressing583.2.4.2 Long-indexed Addressing593.2.4.3 Zero-indexed Addressing593.3 ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS603.3.1 Direct Addressing603.3.2 Indexed Addressing603.4 SOFTWARE STANDARDS AND CONVENTIONS603.4.1 Using Registers603.4.2 Addressing 32-bit Operands613.4.3 Linking Subroutines613.5 SOFTWARE PROTECTION FEATURES AND GUIDELINES62CHAPTER 4 MEMORY PARTITIONS664.1 MEMORY PARTITIONS664.1.1 External Devices (Memory or I/O)664.1.2 Program and Special-purpose Memory664.1.3 Program Memory674.1.4 Special-purpose Memory684.1.4.1 Reserved Memory Locations684.1.4.2 Interrupt and PTS Vectors684.1.4.3 Security Key694.1.4.4 Chip Configuration Bytes (CCBs)694.1.5 Special-function Registers (SFRs)694.1.5.1 Memory-mapped SFRs704.1.5.2 Peripheral SFRs704.1.6 Register File744.1.6.1 General-purpose Register RAM754.1.6.2 Stack Pointer (SP)754.1.6.3 CPU Special-function Registers (SFRs)764.2 WINDOWING774.2.1 Selecting a Window784.2.2 Addressing a Location Through a Window794.2.2.1 32-byte Windowing Example814.2.2.2 64-byte Windowing Example814.2.2.3 128-byte Windowing Example814.2.2.4 Unsupported Locations Windowing Example814.2.2.5 Using the Linker Locator to Set Up a Window824.2.3 Windowing and Addressing Modes84CHAPTER 5 STANDARD AND PTS INTERRUPTS885.1 OVERVIEW OF INTERRUPTS885.2 INTERRUPT SIGNALS AND REGISTERS905.3 INTERRUPT SOURCES AND PRIORITIES915.3.1 Special Interrupts935.3.1.1 Unimplemented Opcode935.3.1.2 Software Trap935.3.1.3 NMI935.3.2 External Interrupt Pin935.3.3 Multiplexed Interrupt Sources945.3.4 End-of-PTS Interrupts965.4 INTERRUPT LATENCY965.4.1 Situations that Increase Interrupt Latency965.4.2 Calculating Latency975.4.2.1 Standard Interrupt Latency975.4.2.2 PTS Interrupt Latency985.5 PROGRAMMING THE INTERRUPTS995.5.1 Modifying Interrupt Priorities1055.5.2 Determining the Source of an Interrupt1075.6 INITIALIZING THE PTS CONTROL BLOCKS1115.6.1 Specifying the PTS Count1125.6.2 Selecting the PTS Mode1145.6.3 Single Transfer Mode1145.6.4 Block Transfer Mode1175.6.5 A/D Scan Mode1195.6.5.1 A/D Scan Mode Cycles1225.6.5.2 A/D Scan Mode Example 11225.6.5.3 A/D Scan Mode Example 21245.6.6 Serial I/O Modes1245.6.6.1 Synchronous SIO Transmit Mode Example1305.6.6.2 Synchronous SIO Receive Mode Example1345.6.6.3 Asynchronous SIO Transmit Mode Example1375.6.6.4 Asynchronous SIO Receive Mode Example142CHAPTER 6 I/O PORTS1486.1 I/O PORTS OVERVIEW1486.2 INPUT-ONLY PORTS 1 (MC, MD ONLY) AND 01496.2.1 Standard Input-only Port Operation1506.2.2 Standard Input-only Port Considerations1516.3 BIDIRECTIONAL PORTS 1 (MH ONLY), 2, 5, AND 7 (MD ONLY)1516.3.1 Bidirectional Port Operation1536.3.2 Bidirectional Port Pin Configurations1566.3.3 Bidirectional Port Pin Configuration Example1586.3.4 Bidirectional Port Considerations1596.4 BIDIRECTIONAL PORTS 3 AND 4 (ADDRESS/DATA BUS)1616.4.1 Bidirectional Ports 3 and 4 (Address/Data Bus) Operation1626.4.2 Using Ports 3 and 4 as I/O1636.4.3 Design Considerations for Ports 3 and 41636.5 STANDARD OUTPUT-ONLY PORT 61636.5.1 Output-only Port Operation1646.5.2 Configuring Output-only Port Pins164CHAPTER 7 SERIAL I/O (SIO) PORT1707.1 SERIAL I/O (SIO) PORT FUNCTIONAL OVERVIEW1707.2 SERIAL I/O PORT SIGNALS AND REGISTERS1717.3 SERIAL PORT MODES1737.3.1 Synchronous Modes (Modes 0 and 4)1747.3.1.1 Mode 01747.3.1.2 Mode 41757.3.2 Asynchronous Modes (Modes 1, 2, and 3)1767.3.2.1 Mode 11767.3.2.2 Mode 21777.3.2.3 Mode 31787.3.2.4 Mode 2 and 3 Timings1787.3.2.5 Multiprocessor Communications1787.4 PROGRAMMING THE SERIAL PORT1797.4.1 Configuring the Serial Port Pins1797.4.2 Programming the Control Register1797.4.3 Programming the Baud Rate and Clock Source1817.4.4 Enabling the Serial Port Interrupts1837.4.5 Determining Serial Port Status184CHAPTER 8 FREQUENCY GENERATOR1888.1 FUNCTIONAL OVERVIEW1888.2 PROGRAMMING THE FREQUENCY GENERATOR1908.2 PROGRAMMING THE FREQUENCY GENERATOR1908.2.2 Programming the Frequency1908.2.3 Determining the Current Value of the Down-counter1918.3 APPLICATION EXAMPLE191CHAPTER 9 WAVEFORM GENERATOR2009.1 WAVEFORM GENERATOR FUNCTIONAL OVERVIEW2009.2 WAVEFORM GENERATOR SIGNALS AND REGISTERS2029.3 WAVEFORM GENERATOR OPERATION2039.3.1 Timebase Generator2039.3.2 Phase Driver Channels2049.3.3 Control and Protection Circuitry2049.3.4 Register Buffering and Synchronization2059.3.5 Operating Modes2069.3.5.1 Center-aligned Modes2089.3.5.2 Edge-Aligned Modes2099.4 PROGRAMMING THE WAVEFORM GENERATOR2119.4.1 Configuring the Outputs2119.4.2 Controlling the Protection Circuitry and EXTINT Interrupt Generation2149.4.3 Specifying the Carrier Period and Duty Cycle2159.4.4 Specifying the Operating Mode and Dead Time and Starting the Counter2169.5 DETERMINING THE WAVEFORM GENERATOR’S STATUS2189.6 ENABLING THE WAVEFORM GENERATOR INTERRUPTS2189.7 DESIGN CONSIDERATIONS2199.7.1 Dead Time and Duty Cycle2199.7.2 EXTINT Interrupts and Protection Circuitry2209.8 PROGRAMMING EXAMPLE220CHAPTER 10 PULSE-WIDTH MODULATOR22810.1 PWM FUNCTIONAL OVERVIEW22810.2 PWM SIGNALS AND REGISTERS22910.3 PWM OPERATION23010.4 PROGRAMMING THE FREQUENCY AND PERIOD23110.5 PROGRAMMING THE DUTY CYCLE23310.5.1 Sample Calculations23410.5.2 Reading the Current Value of the Down-counter23410.5.3 Enabling the PWM Outputs23510.5.4 Generating Analog Outputs237CHAPTER 11 EVENT PROCESSOR ARRAY (EPA)24011.1 EPA FUNCTIONAL OVERVIEW24011.2 EPA AND TIMER/COUNTER SIGNALS AND REGISTERS24111.3 TIMER/COUNTER FUNCTIONAL OVERVIEW24411.3.1 Cascade Mode (Timer 2 Only)24611.3.2 Quadrature Clocking Modes24611.4 EPA CHANNEL FUNCTIONAL OVERVIEW24811.4.1 Operating in Capture Mode24911.4.1.1 EPA Overruns25111.4.1.2 Preventing EPA Overruns25211.4.2 Operating in Compare Mode25211.4.2.1 Generating a Low-speed PWM Output25211.4.2.2 Generating the Highest-speed PWM Output25311.5 PROGRAMMING THE EPA AND TIMER/COUNTERS25411.5.1 Configuring the EPA and Timer/Counter Signals25411.5.2 Programming the Timers25411.5.3 Programming the Capture/Compare Channels25711.5.4 Programming the Compare-only Channels26111.6 ENABLING THE EPA INTERRUPTS26211.7 DETERMINING EVENT STATUS263CHAPTER 12 ANALOG-TO-DIGITAL (A/D) CONVERTER26612.1 A/D CONVERTER FUNCTIONAL OVERVIEW26612.2 A/D CONVERTER SIGNALS AND REGISTERS26712.3 A/D CONVERTER OPERATION26812.4 PROGRAMMING THE A/D CONVERTER26912.4.1 Programming the A/D Test Register27012.4.2 Programming the A/D Result Register (for Threshold Detection Only)27012.4.3 Programming the A/D Time Register27112.4.4 Programming the A/D Command Register27212.4.5 Enabling the A/D Interrupt27312.5 DETERMINING A/D STATUS AND CONVERSION RESULTS27412.6 DESIGN CONSIDERATIONS27512.6.1 Designing External Interface Circuitry27512.6.1.1 Minimizing the Effect of High Input Source Resistance27612.6.1.2 Suggested A/D Input Circuit27712.6.1.3 Analog Ground and Reference Voltages27712.6.1.4 Using Mixed Analog and Digital Inputs27812.6.2 Understanding A/D Conversion Errors278CHAPTER 13 MINIMUM HARDWARE CONSIDERATIONS28613.1 MINIMUM CONNECTIONS28613.1.1 Unused Inputs28713.1.2 I/O Port Pin Connections28713.2 APPLYING AND REMOVING POWER28913.3 NOISE PROTECTION TIPS28913.4 THE ON-CHIP OSCILLATOR CIRCUITRY29013.5 USING AN EXTERNAL CLOCK SOURCE29213.6 RESETTING THE DEVICE29313.6.1 Generating an External Reset29513.6.2 Issuing the Reset (RST) Instruction29713.6.3 Issuing an Illegal IDLPD Key Operand29713.6.4 Generating Wait States29713.6.5 Enabling the Watchdog Timer297CHAPTER 14 SPECIAL OPERATING MODES30214.1 SPECIAL OPERATING MODE SIGNALS AND REGISTERS30214.2 REDUCING POWER CONSUMPTION30414.3 IDLE MODE30514.4 POWERDOWN MODE30614.4.1 Enabling and Disabling Powerdown Mode30614.4.2 Entering Powerdown Mode30714.4.3 Exiting Powerdown Mode30714.4.3.1 Driving the Vpp Pin Low30714.4.3.2 Generating a Hardware Reset30714.4.3.3 Asserting the External Interrupt Signal30814.4.3.4 Selecting R1 and C130914.5 ONCE MODE31114.6 RESERVED TEST MODES312CHAPTER 15 INTERFACING WITH EXTERNAL MEMORY31615.1 EXTERNAL MEMORY INTERFACE SIGNALS AND REGISTERS31615.2 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES32015.3 BUS WIDTH AND MULTIPLEXING32515.3.1 Timing Requirements for BUSWIDTH32815.3.2 16-bit Bus Timings32915.3.3 8-bit Bus Timings33115.4 WAIT STATES (READY CONTROL)33215.5 BUS-CONTROL MODES33615.5.1 Standard Bus-control Mode33715.5.2 Write Strobe Mode34015.5.3 Address Valid Strobe Mode34215.5.4 Address Valid with Write Strobe Mode34515.6 SYSTEM BUS AC TIMING SPECIFICATIONS34615.6.1 Explanation of AC Symbols34815.6.2 AC Timing Definitions348CHAPTER 16 PROGRAMMING THE NONVOLATILE MEMORY35416.1 PROGRAMMING METHODS35416.2 OTPROM MEMORY MAP35516.3 SECURITY FEATURES35616.3.1 Controlling Access to Internal Memory35616.3.1.1 Controlling Access to the OTPROM During Normal Operation35716.3.1.2 Controlling Access to the OTPROM During Programming Modes35716.3.2 Controlling Fetches from External Memory35916.4 PROGRAMMING PULSE WIDTH36116.5 MODIFIED QUICK-PULSE ALGORITHM36216.6 PROGRAMMING MODE PINS36416.7 ENTERING PROGRAMMING MODES36616.7.1 Selecting the Programming Mode36616.7.2 Power-up and Power-down Sequences36716.7.2.1 Power-up Sequence36716.7.2.2 Power-down Sequence36716.8 SLAVE PROGRAMMING MODE36816.8.1 Reading the Signature Word and Programming Voltages36816.8.2 Slave Programming Circuit and Memory Map36916.8.3 Operating Environment37016.8.4 Slave Programming Routines37216.8.5 Timing Mnemonics37716.9 AUTO PROGRAMMING MODE37816.9.1 Auto Programming Circuit and Memory Map37816.9.2 Operating Environment38016.9.3 Auto Programming Routine38016.9.4 Auto Programming Procedure38216.9.5 ROM-dump Mode38316.10 PCCB AND UPROM PROGRAMMING (8XC196MH ONLY)38316.11 RUN-TIME PROGRAMMING385APPENDIX A INSTRUCTION SET REFERENCE390APPENDIX B SIGNAL DESCRIPTIONS450B.1 SIGNAL NAME CHANGES450B.2 FUNCTIONAL GROUPINGS OF SIGNALS450B.3 SIGNAL DESCRIPTIONS461B.4 DEFAULT CONDITIONS471APPENDIX C REGISTERS478GLOSSARY552INDEX566FIGURES29Figure 2-1. 8XC196M x Block Diagram40Figure 2-2. Block Diagram of the Core40Figure 2-3. Clock Circuitry44Figure 2-4. Internal Clock Phases45Figure 4-1. Register File Memory Map74Figure 4-2. Windowing77Figure 4-3. Window Selection (WSR) Register78Figure 5-1. Flow Diagram for PTS and Standard Interrupts89Figure 5-2. Waveform Generator Protection Circuitry94Figure 5-3. Flow Diagram for the OVRTM Interrupt95Figure 5-4. Standard Interrupt Response Time98Figure 5-5. PTS Interrupt Response Time98Figure 5-6. PTS Select (PTSSEL) Register101Figure 5-7. Interrupt Mask (INT_MASK) Register102Figure 5-8. Interrupt Mask 1 (INT_MASK1) Register103Figure 5-9. Peripheral Interrupt Mask (PI_MASK) Register104Figure 5-10. Interrupt Pending (INT_PEND) Register108Figure 5-11. Interrupt Pending 1 (INT_PEND1) Register109Figure 5-12. Peripheral Interrupt Pending (PI_PEND) Register110Figure 5-13. PTS Control Blocks112Figure 5-14. PTS Service (PTSSRV) Register113Figure 5-15. PTS Mode Selection Bits (PTSCON Bits 7:5)114Figure 5-16. PTS Control Block — Single Transfer Mode115Figure 5-17. PTS Control Block — Block Transfer Mode118Figure 5-18. PTS Control Block – A/D Scan Mode120Figure 5-19. PTS Control Block 1 – Serial I/O Mode125Figure 5-20. PTS Control Block 2 – Serial I/O Mode128Figure 5-21. Synchronous SIO Transmit Mode Timing130Figure 5-22. Synchronous SIO Transmit Mode — End-of-PTS Interrupt Routine Flowchart133Figure 5-23. Synchronous SIO Receive Timing134Figure 5-24. Synchronous SIO Receive Mode — End-of-PTS Interrupt Routine Flowchart137Figure 5-25. Asynchronous SIO Transmit Timing138Figure 5-26. Asynchronous SIO Transmit Mode — End-of-PTS Interrupt Routine Flowchart141Figure 5-27. Asynchronous SIO Receive Timing142Figure 5-28. Asynchronous SIO Receive Mode — End-of-PTS Interrupt Routine Flowchart145Figure 6-1. Standard Input-only Port Structure150Figure 6-2. Bidirectional Port Structure155Figure 6-3. Address/Data Bus (Ports 3 and 4) Structure162Figure 6-4. Output-only Port165Figure 6-5. Port 6 Output Configuration (WG_OUTPUT) Register165Figure 7-1. SIO Block Diagram170Figure 7-2. Typical Shift Register Circuit for Mode 0174Figure 7-3. Mode 0 Timing175Figure 7-4. Serial Port Frames for Mode 1177Figure 7-5. Serial Port Frames in Mode 2 and 3178Figure 7-6. Serial Port Control (SP x_CON) Register179Figure 7-7. Serial Port x Baud Rate (SP x_BAUD) Register181Figure 7-8. Serial Port Status (SP x_STATUS) Register184Figure 8-1. Frequency Generator Block Diagram188Figure 8-2. Frequency (FREQ_GEN) Register190Figure 8-3. Frequency Generator Count (FREQ_CNT) Register191Figure 8-4. Infrared Remote Control Application Block Diagram192Figure 8-5. Data Encoding Example192Figure 9-1. Waveform Generator Block Diagram201Figure 9-2. Dead-time Generator Circuitry204Figure 9-3. Protection Circuitry205Figure 9-4. Center-aligned Modes — Counter Operation208Figure 9-5. Center-aligned Modes — Output Operation209Figure 9-6. Edge-aligned Modes — Counter Operation210Figure 9-7. Edge-aligned Modes — Output Operation210Figure 9-8. WG Output Configuration (WG_OUTPUT) Register212Figure 9-9. Waveform Generator Protection (WG_PROTECT) Register214Figure 9-10. Waveform Generator Reload (WG_RELOAD) Register215Figure 9-11. Phase Compare (WG_COMP x) Register216Figure 9-12. Waveform Generator Control (WG_CONTROL) Register217Figure 9-13. Waveform Generator Counter (WG_COUNTER) Register218Figure 9-14. Effect of Dead Time on Duty Cycle219Figure 10-1. PWM Block Diagram229Figure 10-2. PWM Output Waveforms231Figure 10-3. PWM Period (PWM_PERIOD) Register233Figure 10-4. PWM Control (PWMx_CONTROL) Register234Figure 10-5. PWM Count (PWM_COUNT) Register235Figure 10-6. Waveform Generator Output Configuration (WG_OUTPUT) Register236Figure 10-7. D/A Buffer Block Diagram237Figure 10-8. PWM to Analog Conversion Circuitry237Figure 11-1. EPA Block Diagram241Figure 11-2. EPA Timer/Counters245Figure 11-3. Quadrature Mode Interface247Figure 11-4. Quadrature Mode Timing and Count248Figure 11-5. A Single EPA Capture/Compare Channel249Figure 11-6. EPA Simplified Input-capture Structure250Figure 11-7. Valid EPA Input Events250Figure 11-8. Timer 1 Control (T1CONTROL) Register255Figure 11-9. Timer 2 Control (T2CONTROL) Register256Figure 11-10. EPA Control (EPA x_CON) Registers258Figure 11-11. EPA Compare Control (COMP x_CON) Registers261Figure 12-1. A/D Converter Block Diagram266Figure 12-2. A/D Test (AD_TEST) Register270Figure 12-3. A/D Result (AD_RESULT) Register — Write Format271Figure 12-4. A/D Time (AD_TIME) Register272Figure 12-5. A/D Command (AD_COMMAND) Register273Figure 12-6. A/D Result (AD_RESULT) Register — Read Format274Figure 12-7. Idealized A/D Sampling Circuitry275Figure 12-8. Suggested A/D Input Circuit277Figure 12-9. Ideal A/D Conversion Characteristic280Figure 12-10. Actual and Ideal A/D Conversion Characteristics281Figure 12-11. Terminal-based A/D Conversion Characteristic283Figure 13-1. Minimum Hardware Connections288Figure 13-2. Power and Return Connections289Figure 13-3. On-chip Oscillator Circuit290Figure 13-4. External Crystal Connections291Figure 13-5. External Clock Connections292Figure 13-6. External Clock Drive Waveforms292Figure 13-7. Reset Timing Sequence293Figure 13-8. General Configuration Register (GEN_CON)294Figure 13-9. Internal Reset Circuitry295Figure 13-10. Minimum Reset Circuit296Figure 13-11. Example of a System Reset Circuit296Figure 14-1. Clock Control During Power-saving Modes305Figure 14-2. Power-up and Power-down Sequence When Using an External Interrupt308Figure 14-3. External RC Circuit309Figure 14-4. Typical Voltage on the V PP Pin While Exiting Powerdown310Figure 15-1. Chip Configuration 0 (CCR0) Register322Figure 15-2. Chip Configuration 1 (CCR1) Register324Figure 15-3. Multiplexing and Bus Width Options326Figure 15-4. BUSWIDTH Timing Diagram (8XC196MC, MD)327Figure 15-5. BUSWIDTH Timing Diagram (8XC196MH)327Figure 15-6. Timings for 16-bit Buses330Figure 15-7. Timings for 8-bit Buses332Figure 15-8. READY Timing Diagram — One Wait State (8XC196MC, MD)334Figure 15-9. READY Timing Diagram — One Wait State (8XC196MH)335Figure 15-10. Standard Bus Control337Figure 15-11. Decoding WRL# and WRH#337Figure 15-12. 8-bit System with Flash and RAM338Figure 15-13. 16-bit System with Dynamic Bus Width339Figure 15-14. Write Strobe Mode340Figure 15-15. 16-bit System with Writes to Byte-wide RAMs341Figure 15-16. Address Valid Strobe Mode342Figure 15-17. Comparison of ALE and ADV# Bus Cycles342Figure 15-18. 8-bit System with Flash343Figure 15-19. 16-bit System with EPROM344Figure 15-20. Timings of Address Valid with Write Strobe Mode345Figure 15-21. 16-bit System with RAM346Figure 15-22. System Bus Timing347Figure 16-1. Unerasable PROM (USFR) Register360Figure 16-2. Programming Pulse Width (PPW) Register361Figure 16-3. Modified Quick-pulse Algorithm363Figure 16-4. Pin Functions in Programming Modes364Figure 16-5. Slave Programming Circuit369Figure 16-6. Chip Configuration Registers (CCRs)371Figure 16-7. Address/Command Decoding Routine373Figure 16-8. Program Word Routine374Figure 16-9. Program Word Waveform375Figure 16-10. Dump Word Routine376Figure 16-11. Dump Word Waveform377Figure 16-12. Auto Programming Circuit379Figure 16-13. Auto Programming Routine381Figure 16-14. PCCB and UPROM Programming Circuit384Figure 16-15. Run-time Programming Code Example386Figure B-1. 8XC196MC 64-lead Shrink DIP (SDIP) Package452Figure B-2. 8XC196MC 84-lead PLCC Package453Figure B-3. 8XC196MC 80-lead Shrink EIAJ/QFP Package454Figure B-4. 8XC196MD 84-lead PLCC Package456Figure B-5. 8XC196MD 80-lead Shrink EIAJ/QFP Package457Figure B-6. 8XC196MH 64-lead Shrink DIP (SDIP) Package459Figure B-7. 8XC196MH 84-lead PLCC Package460Figure B-8. 8XC196MH 80-lead Shrink EIAJ/QFP Package461TABLES29Table 1-1. Handbooks and Product Information29Table 1-2. Application Notes, Application Briefs, and Article Reprints29Table 1-3. MCS ® 96 Microcontroller Datasheets (Commercial/Express)30Table 1-4. MCS ® 96 Microcontroller Datasheets (Automotive)30Table 1-5. MCS ® 96 Microcontroller Quick References31Table 2-1. Features of the 8XC196Mx Product Family39Table 2-2. State Times at Various Frequencies45Table 3-1. Operand Type Definitions52Table 3-2. Equivalent Operand Types for Assembly and C Programming Languages53Table 3-3. Definition of Temporary Registers57Table 4-1. Memory Map67Table 4-2. Special-purpose Memory Addresses68Table 4-3. Memory-mapped SFRs70Table 4-4. Peripheral SFRs — 8XC196MC71Table 4-5. Peripheral SFRs — 8XC196MD72Table 4-6. Peripheral SFRs — 8XC196MH73Table 4-7. Register File Memory Addresses75Table 4-8. CPU SFRs76Table 4-9. Selecting a Window of Peripheral SFRs78Table 4-10. Selecting a Window of the Upper Register File79Table 4-11. Windows80Table 4-12. Windowed Base Addresses80Table 5-1. Interrupt Signals90Table 5-2. Interrupt and PTS Control and Status Registers90Table 5-3. Interrupt Sources, Vectors, and Priorities92Table 5-4. Execution Times for PTS Cycles99Table 5-5. Single Transfer Mode PTSCB117Table 5-6. Block Transfer Mode PTSCB117Table 5-7. A/D Scan Mode Command/Data Table121Table 5-8. Command/Data Table (Example 1)123Table 5-9. A/D Scan Mode PTSCB (Example 1)123Table 5-10. Command/Data Table (Example 2)124Table 5-11. A/D Scan Mode PTSCB (Example 2)124Table 5-13. SSIO Transmit Mode PTSCBs132Table 5-14. SSIO Receive Mode PTSCBs135Table 5-15. ASIO Transmit Mode PTSCBs139Table 5-16. ASIO Receive Mode PTSCBs143Table 6-1. Device I/O Ports148Table 6-2. Standard Input-only Port Pins149Table 6-3. Input-only Port Registers150Table 6-4. Bidirectional Port Pins152Table 6-5. Bidirectional Port Control and Status Registers153Table 6-6. Logic Table for Bidirectional Ports in I/O Mode156Table 6-7. Logic Table for Bidirectional Ports in Special-function Mode156Table 6-8. Control Register Values for Each Configuration158Table 6-9. Port Configuration Example158Table 6-10. Port Pin States After Reset and After Example Code Execution159Table 6-11. Ports 3 and 4 Pins161Table 6-12. Ports 3 and 4 Control and Status Registers161Table 6-13. Logic Table for Ports 3 and 4 as Open-drain I/O163Table 6-14. Standard Output-only Port Pins164Table 6-15. Output-only Port Control Register164Table 7-1. Serial Port Signals171Table 7-2. Serial Port Control and Status Registers171Table 7-3. SP x_BAUD Values When Using XTAL1 at 16 MHz183Table 8-1. Frequency Generator Signal189Table 8-2. Frequency Generator Control and Status Registers189Table 9-1. Waveform Generator Signals202Table 9-2. Waveform Generator Control and Status Registers202Table 9-3. Operation in Center-aligned and Edge-aligned Modes207Table 9-4. Register Updates207Table 9-5. Output Configuration211Table 10-1. PWM Signals229Table 10-2. PWM Control and Status Registers230Table 10-3. PWM Output Frequencies (Fpwm)232Table 10-4. PWM Output Alternate Functions235Table 11-1. EPA Channels240Table 11-2. EPA and Timer/Counter Signals241Table 11-3. EPA Control and Status Registers242Table 11-4. Quadrature Mode Truth Table247Table 11-5. Action Taken When a Valid Edge Occurs251Table 11-6. Example EPA Control Register Settings for Channels 1, 3, or 5257Table 12-1. A/D Converter Pins267Table 12-2. A/D Control and Status Registers267Table 13-1. Minimum Required Signals286Table 13-2. I/O Port Configuration Guide287Table 13-3. Selecting the Watchdog Reset Interval (8XC196MH only)298Table 14-1. Operating Mode Control Signals302Table 14-2. Operating Mode Control and Status Registers303Table 15-1. External Memory Interface Signals316Table 15-2. External Memory Interface Registers319Table 15-3. Register Settings for Configuring External Memory Interface Signals320Table 15-4. BUSWIDTH Signal Timing Definitions328Table 15-5. READY Signal Timing Definitions335Table 15-6. Bus-control Modes336Table 15-7. AC Timing Symbol Definitions348Table 15-8. External Memory Systems Must Meet These Specifications348Table 15-9. Microcontroller Meets These Specifications349Table 16-1. 87C196Mx OTPROM Memory Map356Table 16-2. Memory Protection for Normal Operating Mode357Table 16-3. Memory Protection Options for Programming Modes358Table 16-4. UPROM Programming Values and Locations for Slave Mode360Table 16-5. Example PPW_VALUE Calculations362Table 16-6. Pin Descriptions364Table 16-7. PMODE Values366Table 16-8. Device Signature Word and Programming Voltages369Table 16-9. Slave Programming Mode Memory Map370Table 16-10. Timing Mnemonics377Table 16-11. 8XC196MC/MD Auto Programming Memory Map380Table 16-12. 8XC196MH Auto Programming Memory Map380Table 16-13. PCCB and UPROM Programming Values385Table A-1. Opcode Map (Left Half)391Table A-2. Processor Status Word (PSW) Flags393Table A-3. Effect of PSW Flags or Specified Conditions on Conditional Jump Instructions394Table A-4. PSW Flag Setting Symbols394Table A-5. Operand Variables395Table A-6. Instruction Set396Table A-7. Instruction Opcodes430Table A-8. Instruction Lengths and Hexadecimal Opcodes436Table A-9. Instruction Execution Times (in State Times)441Table B-1. Signal Name Changes450Table B-2. 8XC196MC Signals Arranged by Functional Categories451Table B-3. 8XC196MD Signals Arranged by Functional Categories455Table B-4. 8XC196MH Signals Arranged by Functional Categories458Table B-5. Description of Columns of Table B-6462Table B-6. Signal Descriptions462Table B-7. Definition of Status Symbols472Table B-8. 8XC196MC and MD Default Signal Conditions472Table B-9. 8XC196MH Default Signal Conditions474Table C-1. Modules and Related Registers478Table C-2. Register Name, Address, and Reset Status479Table C-3. COMP x_TIME Addresses and Reset Values494Table C-4. EPA x_CON Addresses and Reset Values497Tabl e C- 5. EPA x_TIME Addresses and Reset Values498Table C-6. P x_DIR Addresses and Reset Values507Table C-7. P x_MODE Addresses and Reset Values508Table C-8. Special-function Signals for Ports 1, 2, 5, 6509Table C-9. P x_PIN Addresses and Reset Values510Table C-10. P x_REG Addresses and Reset Values511Table C-11. Output Configuration542Table C-12. WSR Settings and Direct Addresses for Windowable SFRs545Tamanho: 4 MBPáginas: 579Language: EnglishAbrir o manual
