ユーザーズマニュアル目次Intel® 41210 Serial to Parallel PCI Bridge1Copyright2Contents3Revision History10Introduction 1111.1 PCI Express* Interface Features111.2 PCI-X Interface Features111.3 Power Management121.4 SMBus Interface121.5 JTAG12Signal Description 2132.1 On-Die Termination (ODT)132.2 PCI Express* Interface152.3 PCI Bus Interface (Two Instances)162.4 PCI Bus Interface 64-Bit Extension (Two Interfaces)182.5 PCI Bus Interface Clocks and, Reset and Power Management (Two Interfaces)182.6 Interrupt Interface (Two Interfaces)192.7 Reset Straps202.8 SMBus Interface212.9 Miscellaneous Pins222.10 Voltage Pins23PCI-X Interface 3253.1 Initialization253.2 Transactions Supported263.2.1 PCI Mode263.2.2 PCI-X Mode273.2.3 Read Transactions273.2.4 Configuration Transactions283.2.5 LOCK Cycles293.2.6 Decoding303.2.7 Transaction Termination303.3 PCI-X Protocol Specifics343.3.1 Attributes343.3.2 4 GB and 4 K Page Crossover343.3.3 Wait States343.3.4 Split Transactions353.4 Arbitration35Power Management 4374.1 Hardware-Controlled Active State Power Management374.2 Software-Driven PCI-PM 1.1-Compatible Power Management374.3 PCI Bus Power Management374.4 Intel® 41210 Serial to Parallel PCI Bridge Device Power Management384.5 Power-Management Event Signaling38Addressing 5415.1 Addressable Spaces within the Intel® 41210 Serial to Parallel PCI Bridge415.2 Secondary PCI Devices425.3 Configuration-Space Access425.3.1 PCI Express* Configuration Access425.3.2 Type 0 Configuration Access from PCI-X Interface445.3.3 SMBus Configuration Access455.4 I/O Space Access Mechanism455.5 Memory Space Access Mechanism475.5.1 Memory-Mapped I/O Window485.5.2 Prefetchable Memory Window495.5.3 Opaque Memory Window495.6 VGA Addressing49Transaction Ordering 6516.1 Upstream Transaction Ordering516.2 Downstream Transaction Ordering526.3 Relaxed Ordering/No-Snoop Support52Interrupt Support 7537.1 Legacy Interrupt Sharing537.2 Interrupt Routing for Devices behind a Bridge54System Management Bus Interface 8558.1 SMBus Commands568.2 Initialization Sequence578.2.1 Configuration578.2.2 Configuration Writes608.3 Error Handling618.4 SMBus Interface Reset62Local Initialization 963Clock and Reset 106510.1 Clocking6510.2 Device Reset6510.2.1 PERST# Reset Mechanism6610.2.2 RSTIN# Reset Mechanism6610.2.3 PCI Express* Reset Mechanism6610.2.4 Software PCI Reset (SBR-Secondary Bus Reset)67Error Handling 116911.1 PCI Express* Errors6911.2 PCI Errors6911.2.1 Error Types7011.2.2 Termination of Completion Required Transactions70Register Description 127312.1 Register Nomenclature and Access Attributes7312.2 Configuration Registers7412.2.1 Offset 00h: ID-Identifiers7812.2.2 Offset 04h: PCICMD-Command Register7812.2.3 Offset 06h: PSTS-Primary Device Status7912.2.4 Offset 08h: REVID-Revision ID8012.2.5 Offset 09h: CC-Class Code8112.2.6 Offset 0Ch: CLS-Cache-Line Size8112.2.7 Offset 0Dh: PMLT-Primary Master Latency Timer8112.2.8 Offset 0Eh: HEADTYP-Header Type8112.2.9 Offset 18h: BNUM-Bus Numbers8212.2.10 Offset 1Bh: SMLT-Secondary Master Latency Timer8212.2.11 Offset 1Ch: IOBL-I/O Base and Limit8312.2.12 Offset 1Eh: SSTS-Secondary Status8412.2.13 Offset 20h: MBL-Memory Base and Limit8512.2.14 Offset 24h: PMBL-Prefetchable Memory Base and Limit8612.2.15 Offset 28h: PMBU32-Prefetchable Memory Base Upper 32 Bits8612.2.16 Offset 2Ch: PMLU32-Prefetchable Memory Limit Upper 32 Bits8712.2.17 Offset 30h: IOBLU16-I/O Base and Limit Upper 16 Bits8712.2.18 Offset 34h: CAPP-Capabilities List Pointer8712.2.19 Offset 3Ch: INTR-Interrupt Information8712.2.20 Offset 3Eh: BCTRL-Bridge Control8812.2.21 Offset 40h: BCNF-Bridge Configuration Register9012.2.22 Offset 42h: MTT-Multi-Transaction Timer9112.2.23 Offset 43h: PCLKC-PCI Clock Control9112.2.24 Offset 44h: EXP_CAPID-PCI Express* Capability Identifier9112.2.25 Offset 45h: EXP_NXTP-Next Item Pointer9112.2.26 Offset 46h: EXP_CAP-PCI Express* Capability9212.2.27 Offset 48h: EXP_DCAP-PCI Express* Device Capabilities Register9212.2.28 Offset 4Ch: EXP_DCTL-PCI Express* Device Control Register9312.2.29 Offset 4Eh: EXP_DSTS-PCI Express* Device Status Register9412.2.30 Offset 50h: EXP_LCAP-PCI Express* Link Capabilities Register9412.2.31 Offset 54h: EXP_LCTL-PCI Express* Link Control Register9512.2.32 Offset 56h: EXP_LSTS-PCI Express* Link Status Register9612.2.33 Offset 5Ch: MSI_CAPID-PCI Express* MSI Capability Identifier9612.2.34 Offset 5Dh: MSI_NXTP-PCI Express* Next Item Pointer9612.2.35 Offset 5Eh: MSI_MC-PCI Express* MSI Message Control9712.2.36 Offset 60h: MSI_MA-PCI Express* MSI Message Address9712.2.37 Offset 68h: MSI_MD-PCI Express* MSI Message Data9712.2.38 Offset 6Ch: PM_CAPID-Power Management Capabilities Identifier9712.2.39 Offset 6Dh: PM_NXTP-Power Management Next Item Pointer9812.2.40 Offset 6Eh: PM_PMC-Power Management Capabilities9812.2.41 Offset 70h: PM_PMCSR-Power Management Control/Status Register9912.2.42 Offset 72h: PM_BSE-Power Management Bridge Support Extensions9912.2.43 Offset 73h: PM_DATA-Power Management Data Field9912.2.44 Offset D8h: PX_CAPID-PCI-X Capabilities Identifier10012.2.45 Offset D9h: PX_NXTP-PCI-X Next Item Pointer10012.2.46 Offset DAh: PX_SSTS-PCI-X Secondary Status10112.2.47 Offset DCh: PX_BSTS-PCI-X Bridge Status10212.2.48 Offset E0h: PX_USTC-PCI-X Upstream Split Transaction Control10212.2.49 Offset E4h: PX_DSTC-PCI-X Downstream Split Transaction Control10312.2.50 Offset FCh: BINIT-Bridge Initialization Register10412.2.51 Offset 100h: EXPAERR_CAPID-PCI Express* Advanced Error Capability Identifier10512.2.52 Offset 104h: ERRUNC_STS-PCI Express* Uncorrectable Error Status Register10512.2.53 Offset 108h: ERRUNC_MSK-PCI Express* Uncorrectable Error Mask10612.2.54 Offset 10Ch: ERRUNC_SEV-PCI Express* Uncorrectable Error Severity10712.2.55 Offset 110h: ERRCOR_STS-PCI Express* Correctable Error Status10812.2.56 Offset 114h: ERRCOR_MSK-PCI Express* Correctable Error Mask10912.2.57 Offset 118h: ADVERR_CTL-Advanced Error Control and Capability Register10912.2.58 Offset 11C-12Bh: HDR_LOG-PCI Express* Transaction Header Log11012.2.59 Offset 12Ch: PCIXERRUNC_STS-Uncorrectable PCI-X Status Register11112.2.60 Offset 130h: PCIXERRUNC_MSK-Uncorrectable PCI-X Error Mask Register11312.2.61 Offset 134h: PCIXERRUNC_SEV-Uncorrectable PCI-X Error Severity Register11512.2.62 Offset 138h: PCIXERRUNC_PTR-Uncorrectable PCI-X Error Pointer11612.2.63 Offset 13C-14Bh: PCIXHDR_LOG-Uncorrectable PCI-X Error Transaction Header Log11712.2.64 Offset 16Ah: ARB_CNTRL-Internal Arbiter Control Register11712.2.65 Offset 170h: SSR-Strap Status Register11812.2.66 Offset 178h: PREFCTRL-Prefetch Control Register11912.2.67 Offset 300h: PWRBGT_CAPID-Power Budgeting Enhanced Capability Header12012.2.68 Offset 304h: PWRBGT_DSEL-Power Budgeting Data Select Register12012.2.69 Offset 308h: PWRBGT_DATA-Power Budgeting Data Register120サイズ: 1.1MBページ数: 120Language: Englishマニュアルを開く