User ManualTable of ContentsFeatures1Available Devices1RISC Processor Background2History2“Soft” FPGA Processors2Why use “Soft” Processors?2Field Reconfigurable Hardware2Faster Time to Market2Improving and Extending Product Life-Cycles3Creating Application-Specific Coprocessors3Implementing Multiple Processors within a Single Device3Lowering System Cost3Avoiding Processor Obsolescence3The ARM720T_LH795203Wishbone Bus Interfaces3Wishbone OpenBUS Processor Wrappers4Processor Abstraction System4Design Migration4Architectural Overview5Symbol5Pin Description6Configuring the Processor8Memory & I/O Management10Defining the Memory Map10Building the Bridge between the Hardware and Software10Dedicated System Interconnect Components12Configuring the Processor12Division of Memory Space12Internal Memory13External Memory14External Memory Interface Time-out14Peripheral I/O14Peripheral I/O Interface Time-out14Data Organization15Words, Half-Words and Bytes15Physical Interface to Memory and Peripherals15Peripheral I/O16Hardware Description17Clocking17Reset17Interrupts17Wishbone Communications18Writing to a Slave Wishbone Peripheral Device18Reading from a Slave Wishbone Peripheral Device18Writing to a Slave Wishbone Memory Device18Reading from a Slave Wishbone Memory Device19Wishbone Timing19Placing an ARM720T_LH79520 in an FPGA design20Design using a Schematic only20Design Featuring an OpenBus System21Facilitating Communications22Additional 'Soft' Devices in Your Design23Enabling the Soft Devices JTAG Chain23Downloading Your Design23On-Chip Debugging24Accessing the Debug Environment24Instruction Set28Revision History28Size: 653 KBPages: 28Language: EnglishOpen manual
