Samsung PM800 - 2.5" SATA 3.0Gb/s MLC SSD 256GB User Manuals

Table of Contents

• 1.0 General Description

  5
• 2.0 Mechanical Specification

  6
  • 2.1 Physical dimensions and Weight

    6
• 3.0 Product Specifications

  7
  • 3.1 System Interface and Configuration

    7
  • 3.2 System Performance

    7
  • 3.3 Drive Capacity

    7
  • 3.4 Supply Voltage

    7
  • 3.5 System Power Consumption*

    7
  • 3.6 System Reliability

    7
  • 3.7 Environmental Specifications

    8
• 4.0 Electrical Interface Specification

  9
  • 4.1 Serial ATA Interface connector

    9
  • 4.2 Pin Assignments

    10
• 5.0 Frame Information Structure (FIS)

  11
  • 5.1 Register - Host to Device

    11
  • 5.2 Register - Device to Host

    12
  • 5.3 Data

    13
  • 5.4 PIO Setup

    13
  • 5.5 DMA Activate - Device to Host

    14
  • 5.6 DMA Setup

    14
  • 5.7 Set Device Bits - Device to Host

    14
• 6.0 Shadow Register Block registers Description

  15
  • 6.1 Command Register

    15
  • 6.2 Device Control Register

    15
    • 6.2.1 1 Field / bit description

      15
  • 6.3 Device / Head Register

    15
    • 6.3.1 1 Field / bit description

      15
  • 6.4 Error Register

    15
    • 6.4.1 1 Field / bit description

      15
  • 6.5 Features Register

    16
  • 6.6 Cylinder High (LBA High) Register

    16
  • 6.7 Cylinder Low (LBA Mid) Register

    16
  • 6.8 Sector Number (LBA low) Register

    16
  • 6.9 Sector Count Register

    16
  • 6.10 Status Register

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    • 6.10.1 1 Field / bit description

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• 7.0 Command Descriptions

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  • 7.1 Supported ATA Commands

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  • 7.2 SECURITY FEATURE Set

    18
    • 7.2.1 1 SECURITY mode default setting

      18
    • 7.2.2 1 Initial setting of the user password

      18
    • 7.2.3 1 SECURITY mode operation from power-on

      18
    • 7.2.4 1 Password lost

      18
  • 7.3 SMART FEATURE Set (B0h)

    18
    • 7.3.1 1 Sub Command

      18
      • 7.3.1.2 S.M.A.R.T. Read Attribute Values (subcommand D0h)

        18
      • 7.3.1.3 S.M.A.R.T. Read Attribute Thresholds (subcommand D1h)

        18
      • 7.3.1.4 S.M.A.R.T. Enable/Disable Attribute Autosave (subcommand D2h)

        19
      • 7.3.1.5 S.M.A.R.T. Save Attribute Values (subcommand D3h)

        19
      • 7.3.1.6 S.M.A.R.T. Execute Off-line Immediate (subcommand D4h)

        19
      • 7.3.1.7 S.M.A.R.T. Selective self-test routine

        20
      • 7.3.1.8 S.M.A.R.T. Read Log Sector (subcommand D5h)

        21
      • 7.3.1.9 S.M.A.R.T. Write Log Sector (subcommand D6h)

        21
      • 7.3.1.10 S.M.A.R.T. Enable Operations (subcommand D8h)

        21
      • 7.3.1.11 S.M.A.R.T. Disable Operations (subcommand D9h)

        21
      • 7.3.1.12 S.M.A.R.T. Return Status (subcommand DAh)

        22
      • 7.3.1.13 S.M.A.R.T. Enable/Disable Automatic Off-line (subcommand DBh)

        22
    • 7.3.2 1 Device Attribute Data Structure

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      • 7.3.2.2 Data Structure Revision Number

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      • 7.3.2.3 Individual Attribute Data Structure

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      • 7.3.2.4 Off-Line Data Collection Status

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      • 7.3.2.5 Self-test execution status

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      • 7.3.2.6 Total time in seconds to complete off-line data collection activity

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      • 7.3.2.7 Current segment pointer

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      • 7.3.2.8 Off-line data collection capability

        25
      • 7.3.2.9 S.M.A.R.T. Capability

        25
      • 7.3.2.10 Error logging capability

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      • 7.3.2.11 Self-test failure check point

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      • 7.3.2.12 Self-test completion time

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      • 7.3.2.13 Data Structure Checksum

        26
    • 7.3.3 1 Device Attribute Thresholds data structure

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      • 7.3.3.2 Data Structure Revision Number

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      • 7.3.3.3 Individual Thresholds Data Structure

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      • 7.3.3.4 Attribute ID Numbers

        26
      • 7.3.3.5 Attribute Threshold

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      • 7.3.3.6 Data Structure Checksum

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    • 7.3.4 1 S.M.A.R.T. Log Directory

      27
    • 7.3.5 1 S.M.A.R.T. error log sector

      27
      • 7.3.5.2 S.M.A.R.T. error log version

        27
      • 7.3.5.3 Error log pointer

        27
      • 7.3.5.4 Device error count

        28
      • 7.3.5.5 Error log data structure

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      • 7.3.5.6 Command data structure

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      • 7.3.5.7 Error data structure

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    • 7.3.6 1 Self-test log structure

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    • 7.3.7 1 Selective self-test log data structure

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    • 7.3.8 1 Error reporting

      31
• 8.0 OOB signaling and Phy Power State

  31
  • 8.1 OOB signaling

    31
    • 8.1.1 1 OOB signal spacing

      31
  • 8.2 Phy Power State

    32
    • 8.2.1 1 COMRESET sequence state diagram

      32
    • 8.2.2 1 Interface Power States

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      • 8.2.2.2 PHYRDY

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      • 8.2.2.3 Partial

        32
      • 8.2.2.4 Slumber

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    • 8.2.3 1 Partial/Slumber to PHYRDY

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      • 8.2.3.2 Host Initiated

        32
      • 8.2.3.3 Device Initiated

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    • 8.2.4 1 PHYRDY to Partial/Slumber

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      • 8.2.4.2 Host Initiated for Partial

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      • 8.2.4.3 Device Initiated for Partial

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• 9.0 SATA II Optional Feature

  34
  • 9.1 Power Segment Pin P11

    34
  • 9.2 Activity LED indication

    34
  • 9.3 Asynchronous Signal Recovery

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• 10.0 Identify Device Data

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• 11.0 Ordering Information

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• 12.0 Product Line up

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