Samsung M393B5670EH1-CF8 User Manuals

Table of Contents

• 1.0 DDR3 Registered DIMM Ordering Information

  5
• 2.0 Key Features

  5
• 3.0 Address Configuration

  5
• 4.0 Registered DIMM Pin Configurations (Front side/Back side)

  6
• 5.0 Pin Description

  7
• 6.0 ON DIMM Thermal Sensor

  7
• 7.0 Input/Output Functional Description

  8
• 8.0 Pinout comparison Based on Module Type

  9
• 9.0 Registering Clock Driver Specification

  10
  • 9.1 Timing & Capacitance values

    10
  • 9.2 Clock driver Characteristics

    10
• 10.0 Functional Block Diagram:

  11
  • 10.1 1GB, 128Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs)

    11
  • 10.2 2GB, 256Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)

    12
  • 10.3 2GB, 256Mx72 module (Populated as 1 rank of x4 DDR3 SDRAMs)

    13
  • 10.4 4GB, 512Mx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs)

    14
  • 10.5 4GB, 512Mx72 Module (Populated as 4 ranks of x8 DDR3 SDRAMs)

    16
  • 10.6 8GB, 1Gx72 Module (Populated as 4 ranks of x4 DDR3 SDRAMs)

    17
• 11.0 Absolute Maximum Ratings

  22
  • 11.1 Absolute Maximum DC Ratings

    22
  • 11.2 DRAM Component Operating Temperature Range

    22
• 12.0 AC & DC Operating Conditions

  22
  • 12.1 Recommended DC Operating Conditions (SSTL - 15)

    22
• 13.0 AC & DC Input Measurement Levels

  23
  • 13.1 AC & DC Logic Input Levels for Single-ended Signals

    23
  • 13.2 VREF Tolerances

    24
  • 13.3 AC and DC Logic Input Levels for Differential Signals

    25
    • 13.3.1 Differential Signals Definition

      25
    • 13.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)

      25
    • 13.3.3 Single-ended Requirements for Differential Signals

      26
    • 13.3.4 Differential Input Cross Point Voltage

      27
  • 13.4 Slew Rate Definition for Single Ended Input Signals

    27
  • 13.5 Slew Rate Definition for Differential Input Signals

    27
• 14.0 AC and DC Output Measurement Levels

  28
  • 14.1 Single Ended AC and DC Output Levels

    28
  • 14.2 Differential AC and DC Output Levels

    28
  • 14.3 Single Ended Output Slew Rate

    28
  • 14.4 Differential Output Slew Rate

    29
• 15.0 IDD specification definition

  30
  • 15.1 IDD SPEC Table

    32
• 16.0 Input/Output Capacitance

  35
• 17.0 Electrical Characteristics and AC timing

  36
  • 17.1 Refresh Parameters by Device Density

    36
  • 17.2 Speed Bins and CL, tRCD, tRC and tRAS for Corresponding Bin

    36
  • 17.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin

    37
    • 17.3.1 Speed Bin Table Notes

      38
• 18.0 Timing Parameters for DDR3-800, DDR3-1066 and DDR3-1333

  39
  • 18.1 Jitter Notes

    42
  • 18.2 Timing Parameter Notes

    43
• 19.0 Physical Dimensions :

  44
  • 19.1 128Mbx8 based 128Mx72 Module(1 Rank) - M393B2873EH1

    44
    • 19.1.1 x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs

      44
  • 19.2 128Mbx8 based 256Mx72 Module(2 Ranks) - M393B5673EH1

    45
    • 19.2.1 x72 DIMM, populated as two physical ranks of x8 DDR3 SDRAMs

      45
  • 19.3 256Mbx4 based 256Mx72 Module(1 Rank) - M393B5670EH1

    46
    • 19.3.1 x72 DIMM, populated as one physical rank of x4 DDR3 SDRAMs

      46
  • 19.4 256Mbx4 based 512Mx72 Module(2 Ranks) - M393B5170EH1

    47
    • 19.4.1 x72 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs

      47
    • 19.4.2 Heat Spreader Design Guide

      48
  • 19.5 128Mbx8 based 512Mx72 Module(4 Ranks) - M393B5173EH1

    50
    • 19.5.1 x72 DIMM, populated as four physical ranks of x8 DDR3 SDRAMs

      50
  • 19.6 512Mbx4 based 1Gx72 Module(4 Ranks) - M393B1G70EM1

    51
    • 19.6.1 x72 DIMM, populated as four physical ranks of x4 DDR3 SDRAMs

      51
    • 19.6.2 Heat Spreader Design Guide

      52