Samsung M378B5673EH1-CF8 User Manuals

Table of Contents

• 1.0 DDR3 Registered DIMM Ordering Information

  5
• 2.0 Key Features

  5
• 3.0 Address Configuration

  5
• 4.0 x64 DIMM Pin Configurations (Front side/Back Side)

  6
• 5.0 x72 DIMM Pin Configurations (Front side/Back side)

  7
• 6.0 Pin Description

  8
• 7.0 SPD and Thermal Sensor for ECC UDIMMs

  8
• 8.0 Input/Output Functional Description

  9
  • 8.1 Address Mirroring Feature

    10
    • 8.1.1 DRAM Pin Wiring Mirroring

      10
• 9.0 Function Block Diagram:

  11
  • 9.1 1GB, 128Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs)

    11
  • 9.2 1GB, 128Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs)

    12
  • 9.3 2GB, 256Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)

    13
  • 9.4 2GB, 256Mx72 ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs)

    14
• 10.0 Absolute Maximum Ratings

  15
  • 10.1 Absolute Maximum DC Ratings

    15
  • 10.2 DRAM Component Operating Temperature Range

    15
• 11.0 AC & DC Operating Conditions

  15
  • 11.1 Recommended DC Operating Conditions (SSTL - 15)

    15
• 12.0 AC & DC Input Measurement Levels

  16
  • 12.1 AC & DC Logic Input Levels for Single-ended Signals

    16
  • 12.2 VREF Tolerances

    17
  • 12.3 AC & DC Logic Input Levels for Differential Signals

    18
    • 12.3.1 Differential Signals Definition

      18
    • 12.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)

      18
    • 12.3.3 Single-ended Requirements for Differential Signals

      19
    • 12.3.4 Differential Input Cross Point Voltage

      20
  • 12.4 Slew Rate Definition for Single-ended Input Signals

    20
  • 12.5 Slew Rate Definition for Differential Input Signals

    20
• 13.0 AC & DC Output Measurement Levels

  21
  • 13.1 Single-ended AC & DC Output Levels

    21
  • 13.2 Differential AC & DC Output Levels

    21
  • 13.3 Single-ended Output Slew Rate

    21
  • 13.4 DIfferential Output Slew Rate

    22
• 14.0 IDD Specification Definition

  23
  • 14.1 IDD SPEC Table

    25
• 15.0 Input/Output Capacitance

  27
  • 15.1 Non ECC UDIMM

    27
  • 15.2 ECC UDIMM

    27
• 16.0 Electrical Characteristics and AC timing

  28
  • 16.1 Refresh Parameters by Device Density

    28
  • 16.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

    28
  • 16.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin

    28
    • 16.3.1 Speed Bin Table Notes

      31
• 17.0 Timing Parameters by Speed Grade

  32
  • 17.1 Jitter Notes

    35
  • 17.2 Timing Parameter Notes

    36
• 18.0 Physical Dimensions

  37
  • 18.1 64Mbx16 based 64Mx64 Module (1 Rank)

    37
  • 18.2 128Mbx8 based 128Mx64/x72 Module (1 Rank)

    38
  • 18.3 128Mbx8 based 256Mx64/x72 Module (2 Ranks)

    39