Lenovo Xeon 1.6GHz User Manuals

Table of Contents

• Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

  1
  • Contents

    3
  • Figures

    4
  • Tables

    5
• 1.0 Introduction

  9
  • Table 1. Features Comparison for Low Voltage Intel® Xeon™ Processors

    10
  • 1.1 Terminology

    10
    • 1.1.1 Processor Packaging Terminology

      10
  • 1.2 State of Data

    11
  • 1.3 References

    11
• 2.0 Electrical Specifications

  13
  • 2.1 System Bus and GTLREF

    13
  • 2.2 Power and Ground Pins

    13
  • 2.3 Decoupling Guidelines

    13
    • 2.3.1 VCC Decoupling

      14
    • 2.3.2 System Bus AGTL+ Decoupling

      14
  • 2.4 System Bus Clock (BCLK[1:0]) and Processor Clocking

    14
    • Table 2. Front Side Bus-to-Core Frequency Ratio

      14
    • 2.4.1 Bus Clock

      15
      • Table 3. System Bus Clock Frequency Select Truth Table for BSEL[1:0]

        15
  • 2.5 PLL Filter

    15
    • Figure 1. Typical VCCIOPLL, VCCA and VSSA Power Distribution

      16
    • Figure 2. Phase Lock Loop (PLL) Filter Requirements

      16
    • 2.5.1 Mixing Processors

      17
  • 2.6 Voltage Identification

    17
    • Table 4. Voltage Identification Definition

      18
    • 2.6.1 Mixing Processors of Different Voltages

      18
  • 2.7 Reserved Or Unused Pins

    19
  • 2.8 System Bus Signal Groups

    19
    • Table 5. System Bus Signal Groups

      20
  • 2.9 Asynchronous GTL+ Signals

    21
  • 2.10 Maximum Ratings

    21
    • Table 6. Processor Absolute Maximum Ratings

      21
  • 2.11 Processor DC Specifications

    22
    • Table 7. Voltage and Current Specifications

      23
    • Figure 3. Low Voltage Intel® Xeon™ Processor Voltage and Current Projections in a Dual-Processor Configuration

      24
    • Table 8. System Bus Differential BCLK Specifications (Sheet 1 of 2)

      24
    • Table 9. AGTL+ Signal Group DC Specifications

      25
    • Table 10. TAP and PWRGOOD Signal Group DC Specifications

      26
    • Table 11. Asynchronous GTL+ Signal Group DC Specifications

      26
  • 2.12 AGTL+ System Bus Specifications

    27
    • Table 12. AGTL+ Bus Voltage Definitions

      27
  • 2.13 System Bus AC Specifications

    27
    • Table 13. System Bus Differential Clock Specifications

      28
    • Table 14. System Bus Common Clock AC Specifications

      29
    • Table 15. System Bus Source Synchronous AC Specifications (Sheet 1 of 2)

      29
    • Table 16. Miscellaneous Signals+ AC Specifications

      30
    • Table 17. System Bus AC Specifications (Reset Conditions)

      31
    • Table 18. TAP Signal Group AC Specifications

      31
  • 2.14 Processor AC Timing Waveforms

    31
    • Figure 4. Electrical Test Circuit

      32
    • Figure 5. TCK Clock Waveform

      32
    • Figure 6. Differential Clock Waveform

      33
    • Figure 7. Differential Clock Crosspoint Specification

      33
    • Figure 8. System Bus Common Clock Valid Delay Timing Waveform

      34
    • Figure 9. System Bus Source Synchronous 2X (Address) Timing Waveform

      34
    • Figure 10. System Bus Source Synchronous 4X (Data) Timing Waveform

      35
    • Figure 11. System Bus Reset and Configuration Timing Waveform

      36
    • Figure 12. Power-On Reset and Configuration Timing Waveform

      36
    • Figure 13. TAP Valid Delay Timing Waveform

      37
    • Figure 14. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform

      37
    • Figure 15. THERMTRIP# to VCC Timing

      37
    • Figure 16. Example 3.3 VDC/VID_VCC Sequencing

      38
• 3.0 System Bus Signal Quality Specifications

  39
  • 3.1 System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines

    39
    • Table 19. BCLK Signal Quality Specifications

      39
    • Figure 17. BCLK[1:0] Signal Integrity Waveform

      40
  • 3.2 System Bus Signal Quality Specifications and Measurement Guidelines

    40
    • Table 20. Ringback Specifications for AGTL+ and Asynchronous GTL+ Buffers

      40
    • Table 21. Ringback Specifications for TAP Buffers

      41
    • Figure 18. Low-to-High System Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+ Buffers

      41
    • Figure 19. High-to-Low System Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+ Buffers

      41
    • Figure 20. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD TAP Buffers

      42
    • Figure 21. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffer

      43
  • 3.3 System Bus Signal Quality Specifications and Measurement Guidelines

    43
    • 3.3.1 Overshoot/Undershoot Guidelines

      43
    • 3.3.2 Overshoot/Undershoot Magnitude

      44
    • 3.3.3 Overshoot/Undershoot Pulse Duration

      44
    • 3.3.4 Activity Factor

      44
    • 3.3.5 Reading Overshoot/Undershoot Specification Tables

      45
    • 3.3.6 Determining When a System Meets the Overshoot/Undershoot Specifications

      45
      • Table 22. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance

        46
      • Table 23. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance

        46
      • Table 24. Common Clock (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance

        47
      • Table 25. 400 MHz Asynchronous GTL+, PWRGOOD, and TAP Signal Groups Overshoot/Undershoot Tolerance (Sheet 1 of 2)

        47
      • Table 26. Source Synchronous (533 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance

        48
      • Table 27. Source Synchronous (533 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (Sheet 1 of 2)

        48
      • Table 28. Common Clock (533 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance

        49
      • Table 29. 533 MHz Asynchronous GTL+, PWRGOOD, and TAP Signal Groups Overshoot/ Undershoot Tolerance

        49
      • Figure 22. Maximum Acceptable Overshoot/Undershoot Waveform

        50
• 4.0 Mechanical Specifications

  51
  • Figure 23. Low Voltage Intel® Xeon™ Processor in the FC-µPGA2 Package: Assembly Drawing

    51
  • 4.1 Mechanical Specifications

    52
    • Figure 24. Low Voltage Intel® Xeon™ Processor in the FC-µPGA2 Package: Top View-Component Placement Detail

      52
    • Figure 25. Low Voltage Intel® Xeon™ Processor in the FC-µPGA2 Package: Drawing

      53
    • Table 30. Dimensions for the Low Voltage Intel® Xeon™ Processor in the FC-µPGA2 Package

      54
    • Figure 26. Low Voltage Intel® Xeon™ Processor in the FC-µPGA2 Package: Top View-Component Height Keep-In

      54
    • Figure 27. Low Voltage Intel® Xeon™ Processor in the FC-µPGA2 Package: Cross Section View, Pin Side Component Keep-In

      55
    • Figure 28. Low Voltage Intel® Xeon™ Processor in the FC-µPGA2 Package: Pin Detail

      55
    • Figure 29. Low Voltage Intel® Xeon™ Processor FC-µPGA2 Package: IHS Flatness and Tilt Drawing

      56
  • 4.2 Processor Package Load Specifications

    56
    • Table 31. Package Dynamic and Static Load Specifications

      56
  • 4.3 Insertion Specifications

    57
  • 4.4 Mass Specifications

    57
    • Table 32. Processor Mass

      57
  • 4.5 Materials

    57
    • Table 33. Processor Material Properties

      57
  • 4.6 Markings

    58
    • Figure 30. Processor Top-Side Markings

      58
    • Figure 31. Processor Bottom-Side Markings

      58
  • 4.7 Processor Pin-Out Diagram

    58
    • Figure 32. Processor Pin Out Diagram: Top View

      59
    • Figure 33. Processor Pin Out Diagram: Bottom View

      60
• 5.0 Pin Listing and Signal Definitions

  61
  • 5.1 Processor Pin Assignments

    61
    • 5.1.1 Pin Listing by Pin Name

      61
      • Table 34. Pin Listing by Pin Name

        61
    • 5.1.2 Pin Listing by Pin Number

      70
      • Table 35. Pin Listing by Pin Number

        70
  • 5.2 Signal Definitions

    79
    • Table 36. Signal Definitions (Sheet 1 of 9)

      79
• 6.0 Thermal Specifications

  89
  • Figure 34. Processor with Thermal and Mechanical Components - Exploded View

    89
  • 6.1 Thermal Specifications

    89
    • Table 37. Processor Thermal Design Power

      90
  • 6.2 Measurements for Thermal Specifications

    90
    • 6.2.1 Processor Case Temperature Measurement

      90
      • Figure 35. Thermal Measurement Point for Processor TCASE

        91
• 7.0 Features

  93
  • 7.1 Power-On Configuration Options

    93
    • Table 38. Power-On Configuration Option Pins

      93
  • 7.2 Clock Control and Low Power States

    93
    • 7.2.1 Normal State-State 1

      93
    • 7.2.2 AutoHALT Powerdown State-State 2

      93
      • Figure 36. Stop Clock State Machine

        94
    • 7.2.3 Stop-Grant State-State 3

      94
    • 7.2.4 HALT/Grant Snoop State-State 4

      95
    • 7.2.5 Sleep State-State 5

      95
    • 7.2.6 Bus Response During Low Power States

      96
  • 7.3 Thermal Monitor

    96
    • 7.3.1 Thermal Diode

      96
  • 7.4 Thermal Diode

    97
    • Table 39. Thermal Diode Parameters

      97
    • Table 40. Thermal Diode Interface

      97
• 8.0 Debug Tools Specifications

  99
  • 8.1 Logic Analyzer Interface (LAI)

    99
    • 8.1.1 Mechanical Considerations

      99
    • 8.1.2 Electrical Considerations

      99
• 9.0 Appendix A

  101
  • 9.1 Processor Core Frequency Determination

    101