Lenovo Intel Xeon Processor E5640 User Manuals

Table of Contents

• 1 Introduction

  7
  • 1.1 References

    7
• 2 Register Description

  9
  • 2.1 Register Terminology

    9
  • 2.2 Platform Configuration Structure

    10
  • 2.3 Device Mapping

    11
  • 2.4 Detailed Configuration Space Maps

    13
  • 2.5 PCI Standard Registers

    36
    • 2.5.1 DID - Device Identification Register

      37
    • 2.5.2 RID - Revision Identification Register

      37
  • 2.6 Generic Non-core Registers

    37
    • 2.6.1 DESIRED_CORES

      37
    • 2.6.2 MIRROR_PORT_CTL

      38
  • 2.7 SAD - System Address Decoder Registers

    39
    • 2.7.1 SAD_MCSEG_BASE

      39
    • 2.7.2 SAD_MCSEG_MASK

      39
    • 2.7.3 SAD_MESEG_BASE

      39
    • 2.7.4 SAD_MESEG_MASK

      40
  • 2.8 Intel QPI Link Registers

    40
    • 2.8.1 QPI_DEF_RMT_VN_CREDITS_L0 QPI_DEF_RMT_VN_CREDITS_L1

      40
    • 2.8.2 QPI_RMT_QPILP1_STAT_L0 QPI_RMT_QPILP1_STAT_L1

      41
    • 2.8.3 MIP_PH_CTR_L0 MIP_PH_CTR_L1

      41
    • 2.8.4 MIP_PH_PRT_L0 MIP_PH_PRT_L1

      42
  • 2.9 Integrated Memory Controller Control Registers

    42
    • 2.9.1 MC_SMI_DIMM_ERROR_STATUS

      43
    • 2.9.2 MC_SMI__CNTRL

      43
    • 2.9.3 MC_MAX_DOD

      44
    • 2.9.4 MC_RD_CRDT_INIT

      45
    • 2.9.5 MC_SCRUBADDR_HI

      46
  • 2.10 Integrated Memory Controller RAS Registers

    46
    • 2.10.1 MC_SSRCONTROL

      46
    • 2.10.2 MC_SCRUB_CONTROL

      46
    • 2.10.3 MC_SSRSTATUS

      47
  • 2.11 Integrated Memory Controller Channel Control Registers

    47
    • 2.11.1 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT

      47
    • 2.11.2 MC_CHANNEL_0_RANK_TIMING_A MC_CHANNEL_1_RANK_TIMING_A MC_CHANNEL_2_RANK_TIMING_A

      48
    • 2.11.3 MC_CHANNEL_0_REFRESH_TIMING MC_CHANNEL_1_REFRESH_TIMING MC_CHANNEL_2_REFRESH_TIMING

      50
    • 2.11.4 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING MC_CHANNEL_2_CKE_TIMING

      51
    • 2.11.5 MC_CHANNEL_0_CKE_TIMING_B MC_CHANNEL_1_CKE_TIMING_B MC_CHANNEL_2_CKE_TIMING_B

      51
    • 2.11.6 MC_CHANNEL_0_SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULER_PARAMS MC_CHANNEL_2_SCHEDULER_PARAMS

      52
    • 2.11.7 MC_CHANNEL_0_PAGETABLE_PARAMS2 MC_CHANNEL_1_PAGETABLE_PARAMS2 MC_CHANNEL_2_PAGETABLE_PARAMS2

      52
  • 2.12 Memory Thermal Control

    53
    • 2.12.1 MC_THERMAL_STATUS0 MC_THERMAL_STATUS1 MC_THERMAL_STATUS2

      53
    • 2.12.2 MC_DDR_THERM0_COMMAND0 MC_DDR_THERM0_COMMAND1 MC_DDR_THERM0_COMMAND2

      53
    • 2.12.3 MC_DDR_THERM1_COMMAND0 MC_DDR_THERM1_COMMAND1 MC_DDR_THERM1_COMMAND2

      54
    • 2.12.4 MC_DDR_THERM0_STATUS0 MC_DDR_THERM0_STATUS1 MC_DDR_THERM0_STATUS2

      54
    • 2.12.5 MC_DDR_THERM1_STATUS0 MC_DDR_THERM1_STATUS1 MC_DDR_THERM1_STATUS2

      55
• 3 Functional Description

  57
  • 3.1 Integrated Memory Controller

    57
  • 3.2 Supported RDIMM Memory Configurations

    58
    • 3.2.1 RDIMM 1.5 V Configurations

      58
    • 3.2.2 RDIMM 1.35 V Configurations

      59
  • 3.3 Supported UDIMM Memory Configurations

    59
    • 3.3.1 UDIMM 1.5V Configurations

      59
    • 3.3.2 UDIMM 1.35V Configurations

      61
  • 3.4 Channel Population Requirements for Memory RAS Modes

    61
  • 3.5 Memory Error Signaling

    62
    • 3.5.1 Enabling SMI/NMI for Memory Corrected Errors

      62
    • 3.5.2 Identifying the Cause of an Interrupt

      62
  • 3.6 DDR_THERM# and DDR_THERM2# Pin Response

    62
  • 3.7 2X Refresh

    63
  • 3.8 Pre-charge Power-Down Slow Exit

    63