User ManualTable of Contents1. Introduction1Chapter Outline12. Product Overview2Intel® Compute Module MFS2600KI Feature Set2Compute Module Layout32.2.1 Connector and Component Locations32.2.2 External I/O Connector Locations43. Functional Architecture5Intel® Xeon® processor53.1.1 Processor Support53.1.2 Processor Initialization Error Summary7Processor Functions Overview93.2.1 Intel® QuickPath Interconnect103.2.2 Intel® Hyper-Threading Technology10Processor Integrated I/O Module (IIO)103.3.1 PCI Express Interfaces103.3.2 DMI2 Interface to the PCH113.3.3 Integrated IOAPIC113.3.4 Intel® QuickData Technology11Memory Subsystem113.4.1 Integrated Memory Controller (IMC) and Memory Subsystem113.4.2 Publishing Compute Module Memory153.4.3 Memory Map and Population Rules153.4.4 Memory RAS19Intel® C602-J Chipset Overvew203.5.1 Digital Media Interface (DMI)213.5.2 PCI Express* Interface213.5.3 Serial ATA (SATA) Controller213.5.4 Low Pin Count (LPC) Interface213.5.5 Serial Peripheral Interface (SPI)213.5.6 Advanced Programmable Interrupt Controller (APIC)213.5.7 Universal Serial Bus (USB) Controllers22Integrated Baseboard Management Controller Overview223.6.1 Super I/O Controller223.6.2 Graphics Controller and Video Support233.6.3 Baseboard Management Controller24Network Interface Controller (NIC)25Intel® Virtualization Technology for Directed I/O (Intel® VT-d)264. System Security27BIOS Password Protection27Trusted Platform Module (TPM) Support28TPM security BIOS28Physical Presence29TPM Security Setup Options29Intel® Trusted Execution Technology305. Connector/Header Locations and Pin-outs31Board Connector Information31Power Connectors31I/O Connector Pin-out Definition32VGA Connector32I/O Mezzanine Card Connector32Midplane Signal Connector36Serial Port Connector37USB 2.0 Connectors37Low Profile eUSB SSD Support386. Jumper Block Settings39CMOS Clear and Password Clear Usage Procedure40Integrated BMC Force Update Procedure41Integrated BMC Initialization41ME Force Update Jumper41BIOS Recovery Jumper427. Product Regulatory Requirements43Product Regulatory Requirements43Product Regulatory Compliance and Safety Markings43Product Environmental/Ecology Requirements43Appendix A: Integration and Usage Tips44Appendix B: POST Code Diagnostic LED Decoder45Appendix C: POST Error Code50Appendix D: Supported Intel® Modular Server System56Glossary57Reference Documents60Figure 1. Component and Connector Location Diagram3Figure 2. Intel® Compute Module MFS2600KI Front Panel Layout4Figure 3. Intel® Compute Module MFS2600KI Functional Block Diagram5Figure 4. Processor Socket Assembly6Figure 5. Intergrated Memory Controller (IMC) and Memory Subsystem11Figure 6. DIMM Slot Order18Figure 7. Integrated BMC Functional Block Diagram22Figure 8. eUSB SSD Support38Figure 9. Recovery Jumper Blocks39Figure 10. POST Code Diagnostic LED Decoder45Figure 11. Intel® Modular Server System MFSYS25V256Table 1. Intel® compute module MFS2600KI Feature Set2Table 2. Mixed Processor Configurations8Table 3. Intel® Compute Module MFS2600KI PCIe Bus Segment Characteristics11Table 4. UDIMM Support Guidelines (Preliminary. Subject to Change)13Table 5. RDIMM Support Guidelines (Preliminary. Subject to Change)14Table 6. LRDIMM Support Guidelines (Preliminary. Subject to Change)14Table 7. DDR3 RDIMM Population within a Channel16Table 8. DDR3L Low Voltage RDIMM Population within a Channel16Table 9. DDR3 UDIMM Population within a Channel17Table 10. DDR3L Low Voltage UDIMM Poplulation within a Channel17Table 11. Intel® Compute Module MFS2600KI DIMM Nomenclature18Table 12. Video Modes23Table 13. Video mode24Table 14. NIC LED BEHAVIOR25Table 15. Board Connector Matrix31Table 16. Power Connector Pin-out (J1A1)31Table 17. VGA Connector Pin-out (J2K1)32Table 18. 120-pin I/O Mezzanine Card Connector Pin-out33Table 19. 120-pin I/O Mezzanine Card Connector Signal Definitions34Table 20. 40-pin I/O Mezzanine Card Connector Pin-out36Table 21. 96-pin Midplane Signal Connector Pin-out36Table 22. Internal 9-pin Serial Header Pin-out (J4K1)37Table 23. External USB Connector Pin-out38Table 24. Pin-out of Internal USB Connector for low-profile Solid State Drive (J1K1)38Table 25. Recovery Jumpers40Table 26. POST Progress Code LED Example45Table 27. POST Progress Codes46Table 28. MRC Progress Codes48Table 29. MRC Fatal Error Codes48Table 30. POST Error Codes and Messages50Table 31. POST Error Beep Codes55Table 32. Integrated BMC Beep Codes55Size: 1.73 MBPages: 67Language: EnglishOpen manual
User ManualTable of Contents1. Introduction1Chapter Outline12. Product Overview2Intel® Compute Module MFS2600KI Feature Set2Compute Module Layout32.2.1 Connector and Component Locations32.2.2 External I/O Connector Locations43. Functional Architecture5Intel® Xeon® processor53.1.1 Processor Support53.1.2 Processor Initialization Error Summary7Processor Functions Overview93.2.1 Intel® QuickPath Interconnect103.2.2 Intel® Hyper-Threading Technology10Processor Integrated I/O Module (IIO)103.3.1 PCI Express Interfaces103.3.2 DMI2 Interface to the PCH113.3.3 Integrated IOAPIC113.3.4 Intel® QuickData Technology11Memory Subsystem113.4.1 Integrated Memory Controller (IMC) and Memory Subsystem113.4.2 Publishing Compute Module Memory153.4.3 Memory Map and Population Rules153.4.4 Memory RAS19Intel® C602-J Chipset Overvew203.5.1 Digital Media Interface (DMI)213.5.2 PCI Express* Interface213.5.3 Serial ATA (SATA) Controller213.5.4 Low Pin Count (LPC) Interface213.5.5 Serial Peripheral Interface (SPI)213.5.6 Advanced Programmable Interrupt Controller (APIC)213.5.7 Universal Serial Bus (USB) Controllers22Integrated Baseboard Management Controller Overview223.6.1 Super I/O Controller223.6.2 Graphics Controller and Video Support233.6.3 Baseboard Management Controller24Network Interface Controller (NIC)25Intel® Virtualization Technology for Directed I/O (Intel® VT-d)264. System Security27BIOS Password Protection27Trusted Platform Module (TPM) Support28TPM security BIOS28Physical Presence29TPM Security Setup Options29Intel® Trusted Execution Technology305. Connector/Header Locations and Pin-outs31Board Connector Information31Power Connectors31I/O Connector Pin-out Definition32VGA Connector32I/O Mezzanine Card Connector32Midplane Signal Connector36Serial Port Connector37USB 2.0 Connectors37Low Profile eUSB SSD Support386. Jumper Block Settings39CMOS Clear and Password Clear Usage Procedure40Integrated BMC Force Update Procedure41Integrated BMC Initialization41ME Force Update Jumper41BIOS Recovery Jumper427. Product Regulatory Requirements43Product Regulatory Requirements43Product Regulatory Compliance and Safety Markings43Product Environmental/Ecology Requirements43Appendix A: Integration and Usage Tips44Appendix B: POST Code Diagnostic LED Decoder45Appendix C: POST Error Code50Appendix D: Supported Intel® Modular Server System56Glossary57Reference Documents60Figure 1. Component and Connector Location Diagram3Figure 2. Intel® Compute Module MFS2600KI Front Panel Layout4Figure 3. Intel® Compute Module MFS2600KI Functional Block Diagram5Figure 4. Processor Socket Assembly6Figure 5. Intergrated Memory Controller (IMC) and Memory Subsystem11Figure 6. DIMM Slot Order18Figure 7. Integrated BMC Functional Block Diagram22Figure 8. eUSB SSD Support38Figure 9. Recovery Jumper Blocks39Figure 10. POST Code Diagnostic LED Decoder45Figure 11. Intel® Modular Server System MFSYS25V256Table 1. Intel® compute module MFS2600KI Feature Set2Table 2. Mixed Processor Configurations8Table 3. Intel® Compute Module MFS2600KI PCIe Bus Segment Characteristics11Table 4. UDIMM Support Guidelines (Preliminary. Subject to Change)13Table 5. RDIMM Support Guidelines (Preliminary. Subject to Change)14Table 6. LRDIMM Support Guidelines (Preliminary. Subject to Change)14Table 7. DDR3 RDIMM Population within a Channel16Table 8. DDR3L Low Voltage RDIMM Population within a Channel16Table 9. DDR3 UDIMM Population within a Channel17Table 10. DDR3L Low Voltage UDIMM Poplulation within a Channel17Table 11. Intel® Compute Module MFS2600KI DIMM Nomenclature18Table 12. Video Modes23Table 13. Video mode24Table 14. NIC LED BEHAVIOR25Table 15. Board Connector Matrix31Table 16. Power Connector Pin-out (J1A1)31Table 17. VGA Connector Pin-out (J2K1)32Table 18. 120-pin I/O Mezzanine Card Connector Pin-out33Table 19. 120-pin I/O Mezzanine Card Connector Signal Definitions34Table 20. 40-pin I/O Mezzanine Card Connector Pin-out36Table 21. 96-pin Midplane Signal Connector Pin-out36Table 22. Internal 9-pin Serial Header Pin-out (J4K1)37Table 23. External USB Connector Pin-out38Table 24. Pin-out of Internal USB Connector for low-profile Solid State Drive (J1K1)38Table 25. Recovery Jumpers40Table 26. POST Progress Code LED Example45Table 27. POST Progress Codes46Table 28. MRC Progress Codes48Table 29. MRC Fatal Error Codes48Table 30. POST Error Codes and Messages50Table 31. POST Error Beep Codes55Table 32. Integrated BMC Beep Codes55Size: 1.73 MBPages: 67Language: EnglishOpen manual