User ManualTable of Contents1.0 Introduction201.1 What You Will Find in This Document201.2 Related Documents202.0 General Description21Figure 1. Block Diagram21Figure 2. Internal Architecture223.0 Ball Assignments and Ball List Tables233.1 Ball Assignments23Figure 3. 552-Ball CBGA Assignments (Top View)233.2 Ball List Tables243.2.1 Balls Listed in Alphabetic Order by Signal Name24Table 1. Ball List in Alphanumeric Order by Signal Name243.2.2 Balls Listed in Alphabetic Order by Ball Location30Table 2. Ball List in Alphanumeric Order by Ball Location304.0 Ball Assignments and Signal Descriptions374.1 Naming Conventions374.1.1 Signal Name Conventions374.1.2 Register Address Conventions374.2 Interface Signal Groups38Figure 4. Interface Signals384.3 Signal Description Tables39Table 3. SPI3 Interface Signal Descriptions (Sheet 1 of 8)39Table 4. SerDes Interface Signal Descriptions47Table 5. GMII Interface Signal Descriptions (Sheet 1 of 2)48Table 6. RGMII Interface Signal Descriptions (Sheet 1 of 2)50Table 7. CPU Interface Signal Descriptions (Sheet 1 of 2)51Table 8. Transmit Pause Control Interface Signal Descriptions53Table 9. Optical Module Interface Signal Descriptions (Sheet 1 of 2)53Table 10. MDIO Interface Signal Descriptions54Table 11. LED Interface Signal Descriptions55Table 12. JTAG Interface Signal Descriptions55Table 13. System Interface Signal Descriptions55Table 14. Power Supply Signal Descriptions564.4 Ball Usage Summary57Table 15. Ball Usage Summary574.5 Multiplexed Ball Connections584.5.1 GMII/RGMII/SerDes/OMI Multiplexed Ball Connections58Table 16. Line Side Interface Multiplexed Balls (Sheet 1 of 2)584.5.2 SPI3 MPHY/SPHY Ball Connections59Table 17. SPI3 MPHY/SPHY Interface (Sheet 1 of 3)594.6 Ball State During Reset61Table 18. Definition of Output and Bi-directional Balls During Hardware Reset (Sheet 1 of 2)614.7 Power Supply Sequencing634.7.1 Power-Up Sequence634.7.2 Power-Down Sequence63Figure 5. Power Supply Sequencing63Table 19. Power Supply Sequencing644.8 Pull-Up/Pull-Down Ball Guidelines64Table 20. Pull-Up/Pull-Down and Unused Ball Guidelines644.9 Analog Power Filtering64Figure 6. Analog Power Supply Filter Network65Table 21. Analog Power Balls655.0 Functional Descriptions665.1 Media Access Controller (MAC)665.1.1 Features for Fiber and Copper Mode675.1.1.1 Padding of Undersized Frames on Transmit675.1.1.2 Automatic CRC Generation675.1.1.3 Filtering of Receive Packets67Table 22. CRC Errored Packets Drop Enable Behavior695.1.1.4 CRC Error Detection695.1.2 Flow Control695.1.2.1 802.3x Flow Control (Full-Duplex Operation)70Figure 7. Packet Buffering FIFO71Figure 8. Ethernet Frame Format71Figure 9. PAUSE Frame Format72Table 23. Valid Decodes for TXPAUSEADD[2:0]74Figure 10. Transmit Pause Control Interface745.1.3 Mixed-Mode Operation755.1.3.1 Configuration755.1.3.2 Key Configuration Registers75Table 24. Operational Mode Configuration Registers765.1.4 Fiber Mode765.1.4.1 Fiber Auto-Negotiation775.1.4.2 Determining If Link Is Established in Auto-Negotiation Mode775.1.4.3 Fiber Forced Mode775.1.4.4 Determination of Link Establishment in Forced Mode775.1.5 Copper Mode775.1.5.1 Speed785.1.5.2 Duplex785.1.5.3 Copper Auto-Negotiation785.1.6 Jumbo Packet Support785.1.6.1 Rx Statistics795.1.6.2 TX Statistics795.1.6.3 Loss-less Flow Control795.1.7 Packet Buffer Dimensions805.1.7.1 TX and RX FIFO Operation805.1.8 RMON Statistics Support80Table 25. RMON Additional Statistics (Sheet 1 of 2)815.1.8.1 Conventions825.1.8.2 Advantages835.2 SPI3 Interface835.2.1 MPHY Operation845.2.1.1 SPI3 RX Round Robin Data Transmission845.2.2 MPHY Logical Timing845.2.2.1 Transmit Timing85Figure 11. MPHY Transmit Logical Timing855.2.2.2 Receive Timing85Figure 12. MPHY Receive Logical Timing86Figure 13. MPHY 32-Bit Interface865.2.2.3 Clock Rates875.2.2.4 Parity875.2.2.5 SPHY Mode875.2.2.6 SPHY Logical Timing885.2.2.7 Transmit Timing (SPHY)88Figure 14. SPHY Transmit Logical Timing885.2.2.8 Receive Timing (SPHY)88Figure 15. SPHY Receive Logical Timing89Figure 16. SPHY Connection for Two Intel® IXF1104 MAC Ports (8-Bit Interface)905.2.2.9 SPI3 Flow Control915.2.3 Pre-Pending Function935.3 Gigabit Media Independent Interface (GMII)93Figure 17. MAC GMII Interconnect945.3.1 GMII Signal Multiplexing945.3.2 GMII Interface Signal Definition94Table 26. GMII Interface Signal Definitions955.4 Reduced Gigabit Media Independent Interface (RGMII)96Figure 18. RGMII Interface965.4.1 Multiplexing of Data and Control965.4.2 Timing Specifics975.4.3 TX_ER and RX_ER Coding97Table 27. RGMII Signal Definitions97Table 28. TX_ER and RX_ER Coding Description97Figure 19. TX_CTL Behavior98Figure 20. RX_CTL Behavior985.4.3.1 In-Band Status995.4.4 10/100 Mbps Functionality995.5 MDIO Control and Interface995.5.1 MDIO Address1005.5.2 MDIO Register Descriptions1005.5.3 Clear When Done1005.5.4 MDC Generation1005.5.4.1 MDC High-Frequency Operation1005.5.4.2 MDC Low-Frequency Operation1005.5.5 Management Frames101Figure 21. Management Frame Structure (Single-Frame Format)1015.5.6 Single MDI Command Operation1015.5.7 MDI State Machine101Figure 22. MDI State1025.5.8 Autoscan Operation1035.6 SerDes Interface1035.6.1 Features1035.6.2 Functional Description1035.6.2.1 Transmitter Operational Overview1045.6.2.2 Transmitter Programmable Driver-Power Levels104Table 29. SerDes Driver TX Power Levels1045.6.2.3 Receiver Operational Overview1055.6.2.4 Selective Power-Down1055.6.2.5 Receiver Jitter Tolerance105Figure 23. SerDes Receiver Jitter Tolerance1065.6.2.6 Transmit Jitter1065.6.2.7 Receive Jitter1065.7 Optical Module Interface1075.7.1 Intel® IXF1104 MAC-Supported Optical Module Interface Signals107Table 30. Intel® IXF1104 MAC-to-SFP Optical Module Interface Connections (Sheet 1 of 2)1075.7.2 Functional Descriptions1085.7.2.1 High-Speed Serial Interface1085.7.2.2 Low-Speed Status Signaling Interface1085.7.3 I·C Module Configuration Interface1105.7.3.1 I2C Control and Data Registers1105.7.3.2 I2C Read Operation110Figure 24. I2C Random Read Transaction1115.7.3.3 I2C Write Operation1115.7.3.4 I·C Protocol Specifics1125.7.3.5 Port Protocol Operation1135.7.3.6 Clock and Data Transitions113Figure 25. Data Validity Timing113Figure 26. Start and Stop Definition Timing113Figure 27. Acknowledge Timing114Figure 28. Random Read1155.8 LED Interface1155.8.1 Modes of Operation1155.8.2 LED Interface Signal Description116Table 31. LED Interface Signal Descriptions1165.8.3 Mode 0: Detailed Operation116Figure 29. Mode 0 Timing116Table 32. Mode 0 Clock Cycle to Data Bit Relationship1175.8.4 Mode 1: Detailed Operation117Figure 30. Mode 1 Timing118Table 33. Mode 1 Clock Cycle to Data Bit Relationship1185.8.5 Power-On, Reset, Initialization1185.8.6 LED DATA Decodes118Table 34. LED_DATA# Decodes1195.8.6.1 LED Signaling Behavior119Table 35. LED Behavior (Fiber Mode)119Table 36. LED Behavior (Copper Mode)1205.9 CPU Interface1205.9.1 Functional Description1215.9.1.1 Read Access121Figure 31. Read Timing Diagram - Asynchronous Interface1215.9.1.2 Write Access121Figure 32. Write Timing Diagram - Asynchronous Interface1225.9.1.3 CPU Timing Parameters1225.9.2 Endian122Table 37. Byte Swapper Behavior1235.10 TAP Interface (JTAG)1235.10.1 TAP State Machine1235.10.2 Instruction Register and Supported Instructions124Table 38. Instruction Register Description1245.10.3 ID Register1255.10.4 Boundary Scan Register1255.10.5 Bypass Register1255.11 Loopback Modes1255.11.1 SPI3 Interface Loopback125Figure 33. SPI3 Interface Loopback Path1265.11.2 Line Side Interface Loopback126Figure 34. Line Side Interface Loopback Path1275.12 Clocks1275.12.1 System Interface Reference Clocks1275.12.1.1 CLK1251285.12.2 SPI3 Receive and Transmit Clocks1285.12.3 RGMII Clocks1285.12.4 MDC Clock1285.12.5 JTAG Clock1295.12.6 I2C Clock1295.12.7 LED Clock1296.0 Applications1306.1 Change Port Mode Initialization Sequence1306.2 Disable and Enable Port Sequences1316.2.1 Disable Port Sequence1316.2.2 Enable Port Sequence1317.0 Electrical Specifications132Table 39. Absolute Maximum Ratings132Table 40. Recommended Operating Conditions1337.1 DC Specifications133Table 41. DC Specifications134Table 42. SerDes Transmit Characteristics (Sheet 1 of 2)134Table 43. SerDes Receive Characteristics1357.1.1 Undershoot / Overshoot Specifications135Table 44. Undershoot / Overshoot Limits1357.1.2 RGMII Electrical Characteristics135Table 45. RGMII Power1367.2 SPI3 AC Timing Specifications1377.2.1 Receive Interface Timing137Figure 35. SPI3 Receive Interface Timing137Table 46. SPI3 Receive Interface Signal Parameters1387.2.2 Transmit Interface Timing139Figure 36. SPI3 Transmit Interface Timing139Table 47. SPI3 Transmit Interface Signal Parameters1407.3 RGMII AC Timing Specification141Figure 37. RGMII Interface Timing141Table 48. RGMII Interface Timing Parameters1417.4 GMII AC Timing Specification1427.4.1 1000 Base-T Operation1427.4.1.1 1000 BASE-T Transmit Interface142Figure 38. 1000BASE-T Transmit Interface Timing142Table 49. GMII 1000BASE-T Transmit Signal Parameters1427.4.1.2 1000BASE-T Receive Interface143Figure 39. 1000BASE-T Receive Interface Timing143Table 50. GMII 1000BASE-T Receive Signal Parameters1437.5 SerDes AC Timing Specification144Figure 40. SerDes Timing Diagram144Table 51. SerDes Timing Parameters1447.6 MDIO AC Timing Specification1457.6.1 MDC High-Speed Operation Timing145Figure 41. MDC High-Speed Operation Timing1457.6.2 MDC Low-Speed Operation Timing145Figure 42. MDC Low-Speed Operation Timing1457.6.3 MDIO AC Timing146Figure 43. MDIO Write Timing Diagram146Figure 44. MDIO Read Timing Diagram146Table 52. MDIO Timing Parameters1467.7 Optical Module and I2C AC Timing Specification1477.7.1 I2C Interface Timing147Figure 45. Bus Timing Diagram147Figure 46. Write Cycle Diagram147Table 53. I2C AC Timing Characteristics (Sheet 1 of 2)1477.8 CPU AC Timing Specification1497.8.1 CPU Interface Read Cycle AC Timing149Figure 47. CPU Interface Read Cycle AC Timing1497.8.2 CPU Interface Write Cycle AC Timing149Figure 48. CPU Interface Write Cycle AC Timing149Table 54. CPU Interface Write Cycle AC Signal Parameters1507.9 Transmit Pause Control AC Timing Specification151Figure 49. Pause Control Interface Timing151Table 55. Transmit Pause Control Interface Timing Parameters1517.10 JTAG AC Timing Specification152Figure 50. JTAG AC Timing152Table 56. JTAG AC Timing Parameters1527.11 System AC Timing Specification153Figure 51. System Reset AC Timing153Table 57. System Reset AC Timing Parameters1537.12 LED AC Timing Specification154Figure 52. LED AC Interface Timing154Table 58. LED Interface AC Timing Parameters1548.0 Register Set1558.1 Document Structure1558.2 Graphical Representation155Figure 53. Memory Overview Diagram1558.3 Per Port Registers156Figure 54. Register Overview Diagram1568.4 Register Map156Table 59. MAC Control Registers ($ Port Index + Offset) (Sheet 1 of 2)156Table 60. MAC RX Statistics Registers ($ Port Index + Offset) (Sheet 1 of 2)157Table 61. MAC TX Statistics Registers ($ Port Index + Offset)158Table 62. PHY Autoscan Registers ($ Port Index + Offset)159Table 63. Global Status and Configuration Registers ($ 0x500 - 0X50C)159Table 64. RX FIFO Registers ($ 0x580 - 0x5BF) (Sheet 1 of 2)159Table 65. TX FIFO Registers ($ 0x600 - 0x63E) (Sheet 1 of 2)160Table 66. MDIO Registers ($ 0x680 - 0x683)161Table 67. SPI3 Registers ($ 0x700 - 0x716) (Sheet 1 of 2)161Table 68. SerDes Registers ($ 0x780 - 0x798)162Table 69. Optical Module Registers ($ 0x799 - 0x79F)1628.4.1 MAC Control Registers163Table 70. Station Address ($ Port_Index +0x00 - +0x01)163Table 71. Desired Duplex ($ Port_Index + 0x02)163Table 72. FD FC Type ($ Port_Index + 0x03)163Table 73. Collision Distance ($ Port_Index + 0x05)164Table 74. Collision Threshold ($ Port_Index + 0x06)164Table 75. FC TX Timer Value ($ Port_Index + 0x07)164Table 76. FD FC Address ($ Port_Index + 0x08 - + 0x09)164Table 77. IPG Receive Time 1 ($ Port_Index + 0x0A)165Table 78. IPG Receive Time 2 ($ Port_Index + 0x0B)165Table 79. IPG Transmit Time ($ Port_Index + 0x0C)165Table 80. Pause Threshold ($ Port_Index + 0x0E)166Table 81. Max Frame Size (Addr: Port_Index + 0x0F)166Table 82. MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)167Table 83. Flush TX ($ Port_Index + 0x11)167Table 84. FC Enable ($ Port_Index + 0x12)168Table 85. FC Back Pressure Length ($ Port_Index + 0x13)168Table 86. Short Runts Threshold ($ Port_Index + 0x14)169Table 87. Discard Unknown Control Frame ($ Port_Index + 0x15)169Table 88. RX Config Word ($ Port_Index + 0x16) (Sheet 1 of 2)169Table 89. TX Config Word ($ Port_Index + 0x17) (Sheet 1 of 2)170Table 90. Diverse Config Write ($ Port_Index + 0x18) (Sheet 1 of 2)171Table 91. RX Packet Filter Control ($ Port_Index + 0x19) (Sheet 1 of 2)172Table 92. Port Multicast Address ($ Port_Index +0x1A - +0x1B)1738.4.2 MAC RX Statistics Register Overview174Table 93. MAC RX Statistics ($ Port_Index + 0x20 - + 0x39) (Sheet 1 of 4)1748.4.3 MAC TX Statistics Register Overview178Table 94. MAC TX Statistics ($ Port_Index +0x40 - +0x58) (Sheet 1 of 4)1788.4.4 PHY Autoscan Registers181Table 95. PHY Control ($ Port Index + 0x60) (Sheet 1 of 2)181Table 96. PHY Status ($ Port Index + 0x61) (Sheet 1 of 2)182Table 97. PHY Identification 1 ($ Port Index + 0x62)183Table 98. PHY Identification 2 ($ Port Index + 0x63)184Table 99. Auto-Negotiation Advertisement ($ Port Index + 0x64) (Sheet 1 of 2)184Table 100. Auto-Negotiation Link Partner Base Page Ability ($ Port Index + 0x65) (Sheet 1 of 2)185Table 101. Auto-Negotiation Expansion ($ Port Index + 0x66) (Sheet 1 of 2)186Table 102. Auto-Negotiation Next Page Transmit ($ Port Index + 0x67)1878.4.5 Global Status and Configuration Register Overview188Table 103. Port Enable ($0x500)188Table 104. Interface Mode ($0x501)188Table 105. Link LED Enable ($0x502)189Table 106. MAC Soft Reset ($0x505)189Table 107. MDIO Soft Reset ($0x506)190Table 108. CPU Interface ($0x508)190Table 109. LED Control ($0x509)190Table 110. LED Flash Rate ($0x50A)191Table 111. LED Fault Disable ($0x50B)191Table 112. JTAG ID ($0x50C)1928.4.6 RX FIFO Register Overview193Table 113. RX FIFO High Watermark Port 0 ($0x580)193Table 114. RX FIFO High Watermark Port 1 ($0x581)193Table 115. RX FIFO High Watermark Port 2 ($0x582)193Table 116. RX FIFO High Watermark Port 3 ($0x583)194Table 117. RX FIFO Low Watermark Port 0 ($0x58A)194Table 118. RX FIFO Low Watermark Port 1 ($0x58B)194Table 119. RX FIFO Low Watermark Port 2 ($0x58C)195Table 120. RX FIFO Low Watermark Port 3 ($0x58D)195Table 121. RX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x594 - 0x597)195Table 122. RX FIFO Port Reset ($0x59E)196Table 123. RX FIFO Errored Frame Drop Enable ($0x59F) (Sheet 1 of 2)196Table 124. RX FIFO Overflow Event ($0x5A0)197Table 125. RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5) (Sheet 1 of 2)198Table 126. RX FIFO SPI3 Loopback Enable for Ports 0 - 3 ($0x5B2)199Table 127. RX FIFO Padding and CRC Strip Enable ($0x5B3)200Table 128. RX FIFO Transfer Threshold Port 0 ($0x5B8)201Table 129. RX FIFO Transfer Threshold Port 1 ($0x5B9)201Table 130. RX FIFO Transfer Threshold Port 2 ($0x5BA)202Table 131. RX FIFO Transfer Threshold Port 3 ($0x5BB)2028.4.7 TX FIFO Register Overview203Table 132. TX FIFO High Watermark Ports 0 - 3 ($0x600 - 0x603)203Table 133. TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A - 0x60D)204Table 134. TX FIFO MAC Threshold Register Ports 0 - 3 ($0x614 - 0x617)205Table 135. TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E) (Sheet 1 of 2)206Table 136. Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F)207Table 137. TX FIFO Port Reset ($0x620) (Sheet 1 of 2)207Table 138. TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 - 0x624)208Table 139. TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 - 0x629)209Table 140. TX FIFO Occupancy Counter for Ports 0 - 3 ($0x62D - 0x630)210Table 141. TX FIFO Port Drop Enable ($0x63D)2108.4.8 MDIO Register Overview211Table 142. MDIO Single Command ($0x680)211Table 143. MDIO Single Read and Write Data ($0x681)211Table 144. Autoscan PHY Address Enable ($0x682)212Table 145. MDIO Control ($0x683)2128.4.9 SPI3 Register Overview213Table 146. SPI3 Transmit and Global Configuration ($0x700) (Sheet 1 of 3)213Table 147. SPI3 Receive Configuration ($0x701) (Sheet 1 of 4)215Table 148. Address Parity Error Packet Drop Counter ($0x70A)2198.4.10 SerDes Register Overview220Table 149. TX Driver Power Level Ports 0 - 3 ($0x784)220Table 150. TX and RX Power-Down ($0x787)220Table 151. RX Signal Detect Level Ports 0 - 3 ($0x793)220Table 152. Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)2218.4.11 Optical Module Register Overview222Table 153. Optical Module Status Ports 0-3 ($0x799)222Table 154. Optical Module Control Ports 0 - 3 ($0x79A)222Table 155. I2C Control Ports 0 - 3 ($0x79B)223Table 156. I2C Data Ports 0 - 3 ($0x79F)2239.0 Mechanical Specifications2249.1 Overview2249.1.1 Features2249.2 Package Specifics2249.3 Package Information2259.3.1 CBGA Package Diagrams225Figure 55. CBGA Package Diagram225Figure 56. CBGA Package Side View Diagram2269.3.2 Flip Chip-Plastic Ball Grid Array Package Diagram227Figure 57. FC-PBGA Package (Top and Bottom Views)227Figure 58. FC-PBGA Mechanical Specifications2289.3.3 Top Label Marking Example229Figure 59. Package Marking Example22910.0 Product Ordering Information230Table 157. Product Information230Figure 60. Ordering Information - Sample231Size: 3.18 MBPages: 231Language: EnglishOpen manual