User ManualTable of Contents8XC251SA, 8XC251SB, 8XC251SP, 8XC251SQ Embedded Microcontroller User’s Manual3CONTENTS5CHAPTER 1 Guide to this Manual211.1 Manual Contents211.2 Notational Conventions and Terminology231.3 Related Documents251.3.1 Data Sheet261.3.2 Application Notes261.4 Application Support Services271.4.1 World Wide Web271.4.2 CompuServe Forums271.4.3 FaxBack Service281.4.4 Bulletin Board System (BBS)28CHAPTER 2 Architectural Overview332.1 8XC251SA, SB, SP, SQ Architecture352.2 MCS 251 Microcontroller Core362.2.1 CPU372.2.2 Clock and Reset Unit382.2.3 Interrupt Handler392.2.4 On-chip Code Memory392.2.5 On-chip RAM392.3 On-chip Peripherals392.3.1 Timer/Counters and Watchdog Timer392.3.2 Programmable Counter Array (PCA)402.3.3 Serial I/O Port40CHAPTER 3 Address Spaces433.1 Address Spaces for MCS® 251 Microcontrollers433.1.1 Compatibility with the MCS® 51 Architecture443.2 8XC251SA, SB, SP, SQ Memory Space473.2.1 On-chip General-purpose Data RAM503.2.2 On-chip Code Memory (83C251SA, SB, SP, SQ/87...503.2.2.1 Accessing On-chip Code Memory in Region 00...513.2.3 External Memory523.3 8XC251SA, SB, SP, SQ Register File523.3.1 Byte, Word, and Dword Registers553.3.2 Dedicated Registers553.3.2.1 Accumulator and B Register553.3.2.2 Extended Data Pointer, DPX563.3.2.3 Extended Stack Pointer, SPX573.4 Special Function Registers (SFRs)58CHAPTER 4 Device Configuration654.1 Configuration Overview654.2 Device Configuration654.3 The Configuration Bits684.4 Configuration Byte Location Selector (UCON)694.5 Configuring the External Memory Interface724.5.1 Page Mode and Nonpage Mode (PAGE#)724.5.2 Configuration Bits RD1:0734.5.2.1 RD1:0 = 00 (18 External Address Bits)734.5.2.2 RD1:0 = 01 (17 External Address Bits)734.5.2.3 RD1:0 = 10 (16 External Address Bits)764.5.2.4 RD1:0 = 11 (Compatible with MCS 51 Microco...764.5.3 Wait State Configuration Bits764.5.3.1 Configuration Bits WSA1:0#, WSB1:#764.5.3.2 Configuration Bit WSB764.5.3.3 Configuration Bit XALE#774.6 Opcode Configurations (SRC)774.6.1 Selecting Binary Mode or Source Mode784.7 Mapping On-chip Code Memory to Data Memory (EM...804.8 Interrupt Mode (INTR)80CHAPTER 5 Programming835.1 Source Mode or Binary Mode Opcodes835.2 Programming Features of the MCS® 251 Architect...835.2.1 Data Types845.2.1.1 Order of Byte Storage for Words and Double...845.2.2 Register Notation845.2.3 Address Notation845.2.4 Addressing Modes865.3 Data Instructions865.3.1 Data Addressing Modes865.3.1.1 Register Addressing875.3.1.2 Immediate875.3.1.3 Direct875.3.1.4 Indirect885.3.1.5 Displacement905.3.2 Arithmetic Instructions905.3.3 Logical Instructions915.3.4 Data Transfer Instructions925.4 Bit Instructions935.4.1 Bit Addressing935.5 Control Instructions945.5.1 Addressing Modes for Control Instructions955.5.2 Conditional Jumps965.5.3 Unconditional Jumps975.5.4 Calls and Returns975.6 Program Status Words98CHAPTER 6 Interrupt System1056.1 OVERVIEW1056.2 8XC251SA, SB, SP, SQ Interrupt Sources1076.2.1 External Interrupts1076.2.2 Timer Interrupts1086.3 Programmable Counter Array (PCA) Interrupt1096.4 SERIAL POrt Interrupt1096.5 Interrupt Enable1096.6 Interrupt Priorities1116.7 Interrupt Processing1136.7.1 Minimum Fixed Interrupt Time1146.7.2 Variable Interrupt Parameters1146.7.2.1 Response Time Variables1146.7.2.2 Computation of Worst-case Latency With Var...1166.7.2.3 Latency Calculations1176.7.2.4 Blocking Conditions1186.7.2.5 Interrupt Vector Cycle1186.7.3 ISRs in Process119CHAPTER 7 Input/Output Ports1237.1 Input/Output port overview1237.2 I/O Configurations1247.3 Port 1 and Port 31247.4 Port 0 and Port 21247.5 Read-Modify-Write Instructions1277.6 Quasi-bidirectional Port Operation1287.7 Port Loading1297.8 External Memory Access129CHAPTER 8 Timer/Counters and WatchDog Timer1358.1 Timer/Counter Overview1358.2 Timer/Counter Operation1358.3 Timer 01378.3.1 Mode 0 (13-bit Timer)1388.3.2 Mode 1 (16-bit Timer)1388.3.3 Mode 2 (8-bit Timer With Auto-reload)1398.3.4 Mode 3 (Two 8-bit Timers)1398.4 Timer 11398.4.1 Mode 0 (13-bit Timer)1438.4.2 Mode 1 (16-bit Timer)1438.4.3 Mode 2 (8-bit Timer with Auto-reload)1438.4.4 Mode 3 (Halt)1438.5 Timer 0/1 Applications1438.5.1 Auto-load Setup Example1438.5.2 Pulse Width Measurements1448.6 Timer 21448.6.1 Capture Mode1458.6.2 Auto-reload Mode1468.6.2.1 Up Counter Operation1468.6.2.2 Up/Down Counter Operation1478.6.3 Baud Rate Generator Mode1488.6.4 Clock-out Mode1488.7 Watchdog Timer1508.7.1 Description1508.7.2 Using the WDT1528.7.3 WDT During Idle Mode1528.7.4 WDT During PowerDown152CHAPTER 9 Programmable Counter Array1559.1 PCA Description1559.1.1 Alternate Port Usage1569.2 PCA Timer/Counter1569.3 PCA Compare/Capture Modules1599.3.1 16-bit Capture Mode1599.3.2 Compare Modes1619.3.3 16-bit Software Timer Mode1619.3.4 High-speed Output Mode1629.3.5 PCA Watchdog Timer Mode1639.3.6 Pulse Width Modulation Mode165CHAPTER 10 Serial I/O Port17310.1 Overview17310.2 Modes of Operation17610.2.1 Synchronous Mode (Mode 0)17610.2.1.1 Transmission (Mode 0)17610.2.1.2 Reception (Mode 0)17710.2.2 Asynchronous Modes (Modes 1, 2, and 3)17810.2.2.1 Transmission (Modes 1, 2, 3)17810.2.2.2 Reception (Modes 1, 2, 3)17810.3 Framing Bit Error Detection (Modes 1, 2, and ...17910.4 Multiprocessor Communication (Modes 2 and 3)17910.5 Automatic Address Recognition17910.5.1 Given Address18010.5.2 Broadcast Address18110.5.3 Reset Addresses18210.6 Baud Rates18210.6.1 Baud Rate for Mode 018210.6.2 Baud Rates for Mode 218210.6.3 Baud Rates for Modes 1 and 318210.6.3.1 Timer 1 Generated Baud Rates (Modes 1 and...18310.6.3.2 Selecting Timer 1 as the Baud Rate Genera...18310.6.3.3 Timer 2 Generated Baud Rates (Modes 1 and...18410.6.3.4 Selecting Timer 2 as the Baud Rate Genera...184CHAPTER 11 Minimum Hardware Setup18911.1 Minimum Hardware Setup18911.2 Electrical Environment19011.2.1 Power and Ground Pins19011.2.2 Unused Pins19011.2.3 Noise Considerations19011.3 Clock Sources19111.3.1 On-chip Oscillator (Crystal)19111.3.2 On-chip Oscillator (Ceramic Resonator)19211.3.3 External Clock19211.4 Reset19311.4.1 Externally Initiated Resets19411.4.2 WDT Initiated Resets19411.4.3 Reset Operation19411.4.4 Power-on Reset195CHAPTER 12 Special Operating Modes19912.1 General19912.2 Power Control Register19912.2.1 Serial I/O Control Bits19912.2.2 Power Off Flag19912.3 Idle Mode20212.3.1 Entering Idle Mode20212.3.2 Exiting Idle Mode20312.4 Powerdown Mode20312.4.1 Entering Powerdown Mode20412.4.2 Exiting Powerdown Mode20412.5 ON-Circuit emulation (Once) Mode20512.5.1 Entering ONCE Mode20512.5.2 Exiting ONCE Mode205CHAPTER 13 External Memory Interface20913.1 Overview20913.2 External Bus Cycles21113.2.1 Bus Cycle Definitions21113.2.2 Nonpage Mode Bus Cycles21213.2.3 Page Mode Bus Cycles21313.3 Wait States21613.4 External Bus Cycles with Configurable Wait St...21613.4.1 Extending RD#/WR#/PSEN#21613.4.2 Extending ALE21813.5 External Bus Cycles with Real-time Wait State...21813.5.1 Real-time WAIT# Enable (RTWE)22013.5.2 Real-time WAIT CLOCK Enable (RTWCE)22013.5.3 Real-time Wait State Bus Cycle Diagrams22013.6 Configuration Byte Bus Cycles22313.7 Port 0 and Port 2 Status22413.7.1 Port 0 and Port 2 Pin Status in Nonpage Mod...22413.7.2 Port 0 and Port 2 Pin Status in Page Mode22513.8 External Memory Design Examples22613.8.1 Example 1: RD1:0 = 00, 18-bit Bus, External...22613.8.2 Example 2: RD1:0 = 01, 17-bit Bus, External...22813.8.3 Example 3: RD1:0 = 01, 17-bit Bus, External...23013.8.4 Example 4: RD1:0 = 10, 16-bit Bus, External...23213.8.5 Example 5: RD1:0 = 11, 16-bit Bus, External...23413.8.5.1 An Application Requiring Fast Access to t...23413.8.5.2 An Application Requiring Fast Access to D...23413.8.6 Example 6: RD1:0 = 11, 16-bit Bus, External...23713.8.7 Example 7: RD1:0 = 01, 17-bit Bus, External...238CHAPTER 14 Programming and Verifying Nonvolatile M...24114.1 General24114.1.1 Programming Considerations for On-chip Code...24214.1.2 EPROM Devices24314.2 Programming and Verifying Modes24314.3 General Setup24314.4 Programming Algorithm24514.5 Verify Algorithm24614.6 Programmable Functions24614.6.1 On-chip Code Memory24714.6.2 Configuration Bytes24714.6.3 Lock Bit System24714.6.4 Encryption Array24814.6.5 Signature Bytes24814.7 Verifying the 83C251SA, SB, SP, SQ (ROM)249APPENDIX A Instruction Set Reference253A.1 Notation for instruction Operands254A.2 Opcode Map and Supporting Tables256A.3 Instruction Set Summary263A.3.1 Execution Times for Instructions that Access...263A.3.2 Instruction Summaries 266A.4 Instruction Descriptions278APPENDIX B Signal Descriptions393APPENDIX C Registers403GLOSSARY439INDEX449FIGURES34Figure 21. Functional Block Diagram of the 8XC251...34Figure 22. The CPU37Figure 23. Clocking Definitions38Figure 31. Address Spaces for MCS® 251 Microcontr...43Figure 32. Address Spaces for the MCS® 51 Archite...45Figure 33. Address Space Mappings MCS® 51 Archite...46Figure 34. 8XC251SA, SB, SP, SQ Address Space48Figure 35. Hardware Implementation of the 8XC251S...49Figure 36. The Register File53Figure 37. Register File Locations 0–754Figure 38. Dedicated Registers in the Register Fi...56Figure 41. Configuration Array (On-chip)66Figure 42. Configuration Array (External)67Figure 43. Configuration Byte UCONFIG070Figure 44. Configuration Byte UCONFIG171Figure 45. Internal/External Address Mapping (RD1...74Figure 46. Internal/External Address Mapping (RD1...75Figure 47. Binary Mode Opcode Map79Figure 48. Source Mode Opcode Map79Figure 51. Word and Double-word Storage in Big En...85Figure 52. Program Status Word Register100Figure 53. Program Status Word 1 Register101Figure 61. Interrupt Control System106Figure 62. Interrupt Enable Register110Figure 63. Interrupt Priority High Register112Figure 64. Interrupt Priority Low Register112Figure 65. The Interrupt Process113Figure 66. Response Time Example #1115Figure 67. Response Time Example #2116Figure 71. Port 1 and Port 3 Structure125Figure 72. Port 0 Structure125Figure 73. Port 2 Structure126Figure 74. Internal Pullup Configurations129Figure 81. Basic Logic of the Timer/Counters136Figure 82. Timer 0/1 in Mode 0 and Mode 1138Figure 83. Timer 0/1 in Mode 2, Auto-Reload139Figure 84. Timer 0 in Mode 3, Two 8-bit Timers140Figure 85. TMOD: Timer/Counter Mode Control Regis...141Figure 86. TCON: Timer/Counter Control Register142Figure 87. Timer 2: Capture Mode145Figure 88. Timer 2: Auto Reload Mode (DCEN = 0)146Figure 89. Timer 2: Auto Reload Mode (DCEN = 1)147Figure 810. Timer 2: Clock Out Mode149Figure 811. T2MOD: Timer 2 Mode Control Register150Figure 812. T2CON: Timer 2 Control Register151Figure 91. Programmable Counter Array157Figure 92. PCA 16-bit Capture Mode160Figure 93. PCA Software Timer and High-speed Outp...162Figure 94. PCA Watchdog Timer Mode164Figure 95. PCA 8-bit PWM Mode165Figure 96. PWM Variable Duty Cycle166Figure 97. CMOD: PCA Timer/Counter Mode Register167Figure 98. CCON: PCA Timer/Counter Control Regist...168Figure 99. CCAPMx: PCA Compare/Capture Module Mod...169Figure 101. Serial Port Block Diagram174Figure 102. SCON: Serial Port Control Register175Figure 103. Mode 0 Timing177Figure 104. Data Frame (Modes 1, 2, and 3) 178Figure 105. Timer 2 in Baud Rate Generator Mode185Figure 111. Minimum Setup189Figure 112. CHMOS On-chip Oscillator191Figure 113. External Clock Connection192Figure 114. External Clock Drive Waveforms193Figure 115. Reset Timing Sequence196Figure 121. Power Control (PCON) Register200Figure 122. Idle and Powerdown Clock Control201Figure 131. Bus Structure in Nonpage Mode and Pag...209Figure 132. External Code Fetch (Nonpage Mode)212Figure 133. External Data Read (Nonpage Mode)212Figure 134. External Data Write (Nonpage Mode)213Figure 135. External Code Fetch (Page Mode)214Figure 136. External Data Read (Page Mode)215Figure 137. External Data Write (Page Mode)215Figure 138. External Code Fetch (Nonpage Mode, On...217Figure 139. External Data Write (Nonpage Mode, On...217Figure 1310. External Code Fetch (Nonpage Mode, O...218Figure 1311. Real-time Wait State Control Registe...219Figure 1312. External Code Fetch/Data Read (Nonpa...221Figure 1313. External Data Write (Nonpage Mode, R...221Figure 1314. External Data Read (Page Mode, RT Wa...222Figure 1315. External Data Write (Page Mode, RT W...222Figure 1316. Configuration Byte Bus Cycles223Figure 1317. Bus Diagram for Example 1: 80C251SB ...226Figure 1318. Address Space for Example 1227Figure 1319. Bus Diagram for Example 2: 80C251SB ...228Figure 1320. Address Space for Example 2229Figure 1321. Bus Diagram for Example 3: 87C251SB/...230Figure 1322. Address Space for Example 3231Figure 1323. Bus Diagram for Example 4: 87C251SB/...232Figure 1324. Address Space for Example 4233Figure 1325. Bus Diagram for Example 5: 80C251SB ...235Figure 1326. Address Space for Examples 5 and 6236Figure 1327. Bus Diagram for Example 6: 80C251SB ...237Figure 1328. Bus Diagram for Example 7: 80C251SB ...238Figure 141. Setup for Programming and Verifying N...245Figure 142. Program/Verify Bus Cycles246Figure B1. 8XC251SA, SB, SP, SQ 44-pin PLCC Packa...393Figure B2. 8XC251SA, SB, SP, SQ 40-pin PDIP and C...395TABLES27Table 11. Intel Application Support Services27Table 21. 8XC251SA, SB, SP, SQ Features35Table 31. Address Mappings46Table 32. Minimum Times to Fetch Two Bytes of Cod...51Table 33. Register Bank Selection54Table 34. Dedicated Registers in the Register Fil...57Table 35. 8XC251SA, SB, SP, SQ SFR Map and Reset ...59Table 36. Core SFRs60Table 37. I/O Port SFRs60Table 38. Serial I/O SFRs61Table 39. Timer/Counter and Watchdog Timer SFRs61Table 310. Programmable Counter Array (PCA) SFRs...61Table 41. External Addresses for Configuration Ar...68Table 42. Memory Signal Selections (RD1:0)72Table 43. RD#, WR#, PSEN# External Wait States77Table 44. Examples of Opcodes in Binary and Sourc...78Table 51. Data Types84Table 52. Notation for Byte Registers, Word Regis...85Table 53. Addressing Modes for Data Instructions ...88Table 54. Addressing Modes for Data Instructions ...89Table 55. Bit-addressable Locations93Table 56. Addressing Two Sample Bits94Table 57. Addressing Modes for Bit Instructions94Table 58. Addressing Modes for Control Instructio...95Table 59. Compare-conditional Jump Instructions96Table 510. The Effects of Instructions on the PSW...99Table 61. Interrupt System Pin Signals105Table 62. Interrupt System Special Function Regis...107Table 63. Interrupt Control Matrix108Table 64. Level of Priority111Table 65. Interrupt Priority Within Level111Table 66. Interrupt Latency Variables117Table 67. Actual vs. Predicted Latency Calculatio...117Table 71. Input/Output Port Pin Descriptions 123Table 72. Instructions for External Data Moves131Table 81. Timer/Counter and Watchdog Timer SFRs136Table 82. External Signals137Table 83. Timer 2 Modes of Operation149Table 91. PCA Special Function Registers (SFRs)158Table 92. External Signals158Table 93. PCA Module Modes168Table 101. Serial Port Signals173Table 102. Serial Port Special Function Registers...174Table 103. Summary of Baud Rates182Table 104. Timer 1 Generated Baud Rates for Seria...184Table 105. Selecting the Baud Rate Generator(s)185Table 106. Timer 2 Generated Baud Rates186Table 121. Pin Conditions in Various Modes201Table 131. External Memory Interface Signals210Table 132. Bus Cycle Definitions (No Wait States)...211Table 133. Port 0 and Port 2 Pin Status In Normal...224Table 141. Programming and Verifying Modes 244Table 142. Lock Bit Function248Table 143. Contents of the Signature Bytes249Table A1. Notation for Register Operands254Table A2. Notation for Direct Addresses255Table A3. Notation for Immediate Addressing255Table A4. Notation for Bit Addressing255Table A5. Notation for Destinations in Control In...255Table A6. Instructions for MCS® 51 Microcontrolle...256Table A7. New Instructions for the MCS® 251 Archi...257Table A8. Data Instructions258Table A9. High Nibble, Byte 0 of Data Instruction...258Table A10. Bit Instructions259Table A11. Byte 1 (High Nibble) for Bit Instructi...259Table A12. PUSH/POP Instructions260Table A13. Control Instructions260Table A14. Displacement/Extended MOVs261Table A15. INC/DEC262Table A16. Encoding for INC/DEC262Table A17. Shifts262Table A18. State Times to Access the Port SFRs(C...264Table A19. Summary of Add and Subtract Instructio...266Table A20. Summary of Compare Instructions267Table A21. Summary of Increment and Decrement Ins...268Table A22. Summary of Multiply, Divide, and Decim...268Table A23. Summary of Logical Instructions (Conti...269Table A24. Summary of Move Instructions (Continue...271Table A25. Summary of Exchange, Push, and Pop Ins...274Table A26. Summary of Bit Instructions 275Table A27. Summary of Control Instructions (Conti...276Table A28. Flag Symbols278Table B1. PLCC/DIP Pin Assignments Listed by Func...394Table B2. Signal Descriptions (Continued)395Table B3. Memory Signal Selections (RD1:0)399Table C1. 8XC251SA, SB, SP, SQ SFR Map404Table C2. Core SFRs405Table C3. I/O Port SFRs405Table C4. Serial I/O SFRs406Table C5. Timer/Counter and Watchdog Timer SFRs406Table C6. Programmable Counter Array (PCA) SFRs...407Table C7. Register File408Size: 2.59 MBPages: 458Language: EnglishOpen manual