User ManualTable of Contents1 Introduction131.1 System Overview131.1.1 Component Overview141.2 Product Features151.3 Itanium™ Processor System Bus Support151.4 DRAM Interface Support161.5 I/O Support161.5.1 PXB Features161.5.2 WXB Features171.5.3 GXB Features171.6 RAS Features171.7 Other Platform Components181.7.1 I/O & Firmware Bridge (IFB)181.7.2 Programmable Interrupt Device (PID)181.8 Reference Documents181.9 Revision History192 Register Descriptions212.1 Access Mechanism212.2 Access Restrictions222.2.1 Partitioning222.2.2 Register Attributes232.2.3 Reserved Bits Defined in Registers232.2.4 Reserved or Undefined Register Locations232.2.5 Default Upon Reset232.2.6 Consistency242.2.7 GART Programming Region242.3 I/O Mapped Registers242.3.1 CONFIG_ADDRESS: Configuration Address Register242.3.2 CONFIG_DATA: Configuration Data Register252.4 Error Handling Registers252.4.1 SAC252.4.2 SDC312.4.3 MAC412.4.4 PXB422.4.5 GXB442.4.6 WXB472.5 Performance Monitor Registers502.5.1 SAC502.5.2 SDC542.5.3 PXB562.5.4 GXB582.5.5 WXB632.6 Interrupt Related Registers642.6.1 SAC642.6.2 PID PCI Memory-mapped Registers652.6.3 PID Indirect Access Registers663 System Architecture733.1 Coherency733.1.1 Processor Coherency733.1.2 PCI Coherency743.1.3 AGP Coherency743.2 Ordering743.3 Processor to PCI Traffic and PCI to PCI (Peer-to- Peer) Traffic753.4 WXB Arbitration753.5 Big-endian Support763.6 Indivisible Operations763.6.1 Processor Locks763.6.2 Inbound PCI Locks773.6.3 Atomic Writes773.6.4 Atomic Reads773.6.5 Locks with AGP Non-coherent Traffic773.7 Interrupt Delivery783.8 WXB PCI Hot-Plug Support783.8.1 Slot Power-up and Enable793.8.2 Slot Power-down and Disable794 System Address Map814.1 Memory Map814.1.1 Compatibility Region814.1.2 Low Extended Memory Region834.1.3 Medium Extended Memory Region834.1.4 High Extended Memory (above 4G)844.1.5 Re-mapped Memory Areas844.2 I/O Address Map854.3 Devices View of the System Memory Map874.4 Legal and Illegal Address Disposition885 Memory Subsystem915.1 Organization915.1.1 DIMM Types935.2 Interleaving/Configurations945.2.1 Summary of Configuration Rules955.2.2 Non-uniform Memory Configurations955.3 Bandwidth955.4 Memory Subsystem Clocking965.5 Supporting Features965.5.1 Auto Detection965.5.2 Removing a Bad Row965.5.3 Hardware Initialization975.5.4 Memory Scrubbing976 Data Integrity and Error Handling996.1 Integrity996.1.1 System Bus996.1.2 DRAM1006.1.3 Expander Buses1006.1.4 PCI Buses1006.1.5 AGP1006.1.6 Private Bus between SAC and SDC1006.2 Memory ECC Routing1016.3 Data Poisoning1016.4 Usage of First-error and Next-error1016.4.1 Masked Bits1026.4.2 BERR#/BINIT# Generation1026.4.3 INTREQ#1026.4.4 XBINIT#1036.4.5 XSERR#1036.5 SAC/SDC Errors1036.5.1 Data ECC or Parity Errors1036.5.2 System Bus Errors1046.5.3 SAC to SDC Interface Errors1046.5.4 SAC to MAC Interface Errors1056.5.5 SDC/Memory Card Interface Errors1056.5.6 SDC/System Bus Errors1066.5.7 SDC Internal Errors1066.6 Error Determination1066.6.1 SAC Address on an Error1076.6.2 SDC Logging Registers1086.7 Clearing Errors1096.7.1 SAC/SDC Error Clearing1096.8 Multiple Errors1096.8.1 SDC Multiple Errors1106.8.2 SAC Multiple Errors1116.8.3 Single Errors with Multiple Reporting1116.8.4 Error Anomalies1116.9 Data Flow Errors1126.10 Error Conditions1136.10.1 Table of Errors1136.11 PCI Integrity1186.11.1 PCI Bus Monitoring1186.11.2 PXB as Master1186.11.3 PXB as Target1196.11.4 GXB Error Flow1206.12 WXB Data Integrity and Error Handling1246.12.1 Integrity1246.12.2 Data Parity Poisoning1246.12.3 Usage of First Error and Next Error Registers1246.12.4 Error Mask Bits1256.12.5 Error Steering/Signaling1256.12.6 INTRQ# Interrupt1276.12.7 Error Determination and Logging1276.12.8 Error Conditions1287 AGP Subsystem1317.1 Graphics Address Relocation Table (GART)1317.1.1 GART Implementation1337.1.2 Programming GART1347.1.3 GART Implementation1357.1.4 Coherency1357.1.5 Interrupt Handling1367.2 AGP Traffic1367.2.1 Addresses Used by the Graphics Card1367.2.2 Traffic Priority1377.2.3 Coherency, Translation and Types of AGP Traffic1377.2.4 Ordering Rules1387.2.5 Processor Locks and AGP Traffic1387.2.6 Address Alignment and Transfer Sizes1397.2.7 PCI Semantics Traffic1397.3 Bandwidth1437.3.1 Inbound Read Prefetching1447.4 Latency1447.5 GXB Address Map1448 WXB Hot-Plug1478.1 IHPC Configuration Registers1478.1.1 Page Number List for the IHPC PCI Register Descriptions1498.1.2 VID: Vendor Identification Register1498.1.3 DID: Device Identification Register1498.1.4 PCICMD: PCI Command Register1508.1.5 PCISTS: PCI Status Register1518.1.6 RID: Revision Identification Register1518.1.7 CLASS: Class Register1528.1.8 CLS: Cache Line Size1528.1.9 MLT: Master Latency Timer Register1528.1.10 HDR: Header Register1528.1.11 Base Address1538.1.12 SVID: Subsystem Vendor Identification1538.1.13 SID: Subsystem ID1538.1.14 Interrupt Line1538.1.15 Interrupt Pin1548.1.16 Hot-Plug Slot Identifier1548.1.17 Miscellaneous Hot-Plug Configuration1548.1.18 Hot-Plug Features1558.1.19 Switch Change SERR Status1558.1.20 Power Fault SERR Status1558.1.21 Arbiter SERR Status1568.1.22 Memory Access Index1568.1.23 Memory Mapped Register Access Port1568.2 IHPC Memory Mapped Registers1568.2.1 Page Number List for IHPC Memory Mapped Register Descriptions1588.2.2 Slot Enable1588.2.3 Hot-Plug Miscellaneous1598.2.4 LED Control1598.2.5 Hot-Plug Interrupt Input and Clear1608.2.6 Hot-Plug Interrupt Mask1618.2.7 Serial Input Byte Data1628.2.8 Serial Input Byte Pointer1638.2.9 General Purpose Output1638.2.10 Hot-Plug Non-interrupt Inputs1638.2.11 Hot-Plug Slot Identifier1638.2.12 Hot-Plug Switch Interrupt Redirect Enable1648.2.13 Slot Power Control1648.2.14 Extended Hot-Plug Miscellaneous1649 IFB Register Mapping1659.1 PCI / LPC / FWH Configuration1659.1.1 PCI Configuration Registers (Function 0)1659.2 IDE Configuration1679.2.1 PCI Configuration Registers (Function 1)1679.3 Universal Serial Bus (USB) Configuration1689.3.1 PCI Configuration Registers (Function 2)1689.4 SMBus Controller Configuration1699.4.1 SMBus Configuration Registers (Function 3)16910 IFB Usage Considerations17110.1 Usage of 1MIN Timer in Power Management17110.2 Usage of the SW SMI# Timer17110.3 CD-ROM AUTO RUN Feature of the OS17110.4 ACPI, SMBus, GPIO Base Address Reporting to the OS17110.5 Ultra DMA Configuration17210.5.1 UDMAC–Ultra DMA Control Register (IFB Function 1 PCI Configuration Offset 48h)17210.5.2 UDMATIM–Ultra DMA Timing Register (IFB Function 1 PCI Configuration Offsets 4A-4Bh)17210.5.3 Determining a Drive’s Transfer Rate Capabilities17310.5.4 Determining a Drive’s Best Ultra DMA Capability17510.5.5 Determining a Drive’s Best Multi Word DMA/Single Word DMA (Non-ultra DMA) Capability17510.5.6 IFB Timing Settings17910.5.7 Drive Configuration for Selected Timings18110.5.8 Settings Checklist18310.5.9 Example Configurations18410.5.10 Ultra DMA System Software Considerations18610.5.11 Additional Ultra DMA/PCI Bus Master IDE Device Driver Considerations18710.6 USB Resume Enable Bit18911 LPC/FWH Interface Configuration19111.1 PCI to LPC/FWH Interface Configuration Space Registers (PCI Function 0)19111.1.1 VID–Vendor Identification Register (Function 0)19111.1.2 DID–Device Identification Register (Function 0)19111.1.3 PCICMD–PCI Command Register (Function 0)19211.1.4 PCISTS–PCI Device Status Register (Function 0)19211.1.5 RID–Revision Identification Register (Function 0)19311.1.6 CLASSC–Class Code Register (Function 0)19311.1.7 HEDT–Header Type Register (Function 0)19311.1.8 ACPI Base Address (Function 0)19411.1.9 ACPI Enable (Function 0)19411.1.10 SCI IRQ Routing Control19411.1.11 BIOSEN–BIOS Enable Register (Function 0)19511.1.12 PIRQRC[A:D]–PIRQx Route Control Registers (Function 0)19511.1.13 SerIRQC–Serial IRQ Control Register (Function 0)19611.1.14 TOM–Top of Memory Register (Function 0)19611.1.15 MSTAT–Miscellaneous Status Register (Function 0)19711.1.16 Deterministic Latency Control Register (Function 0)19711.1.17 MGPIOC–Muxed GPIO Control (Function 0)19811.1.18 PDMACFG–PCI DMA Configuration Resister (Function O)19811.1.19 DDMABP–Distributed DMA Slave Base Pointer Registers (Function 0)19811.1.20 RTCCFG–Real Time Clock Configuration Register (Function 0)19911.1.21 GPIO Base Address (Function 0)20011.1.22 GPIO Enable (Function 0)20011.1.23 LPC COM Decode Ranges (Function 0)20011.1.24 LPC FDD/LPT Decode Ranges (Function 0)20111.1.25 LPC Sound Decode Ranges (Function 0)20211.1.26 LPC Generic Decode Range (Function 0)20211.1.27 LPC Enables (Function 0)20311.2 PCI to LPC I/O Space Registers20511.2.1 DMA Registers20511.2.2 Interrupt Controller Registers21011.2.3 Counter/Timer Registers21511.2.4 NMI Registers21811.2.5 Real Time Clock Registers21911.2.6 Advanced Power Management (APM) Registers22011.2.7 ACPI Registers22111.2.8 SMI Registers22511.2.9 General Purpose I/O Registers22712 IDE Configuration23312.1 PCI Configuration Registers (Function 1)23312.2 IDE Controller Register Descriptions (PCI Function 1)23312.2.1 VID–Vendor Identification Register (Function 1)23412.2.2 DID–Device Identification Register (Function 1)23412.2.3 PCICMD–PCI Command Register (Function 1)23412.2.4 PCISTS–PCI Device Status Register (Function 1)23512.2.5 CLASSC–Class Code Register (Function 1)23512.2.6 MLT–Master Latency Timer Register (Function 1)23612.2.7 BMIBA–Bus Master Interface Base Address Register (Function 1)23612.2.8 SVID–Subsystem Vendor ID (Function 1)23712.2.9 SID–Subsystem ID (Function 1)23712.2.10 IDETIM–IDE Timing Register (Function 1)23712.2.11 SIDETIM–Slave IDE Timing Register (Function 1)23812.2.12 DMACTL–Synchronous DMA Control Register (Function 1)23912.2.13 SDMATIM–Synchronous DMA Timing Register (Function 1)24012.3 IDE Controller I/O Space Registers24112.3.1 BMICx–Bus Master IDE Command Register (I/O)24112.3.2 BMISx–Bus Master IDE Status Register (I/O)24212.3.3 BMIDTPx–Bus Master IDE Descriptor Table Pointer Register (I/O)24313 Universal Serial Bus (USB) Configuration24513.1 PCI Configuration Registers (Function 2)24513.2 USB Host Controller Register Descriptions (PCI Function 2)24613.2.1 VID–Vendor Identification Register (Function 2)24613.2.2 DID–Device Identification Register (Function 2)24613.2.3 PCICMD–PCI Command Register (Function 2)24613.2.4 PCISTS–PCI Device Status Register (Function 2)24713.2.5 RID–Revision Identification Register (Function 2)24713.2.6 CLASSC–Class Code Register (Function 2)24813.2.7 MLT–Master Latency Timer Register (Function 2)24813.2.8 HEDT–Header Type Register (Function 2)24813.2.9 USBBA–USB I/O Space Base Address (Function 2)24913.2.10 SVID–Subsystem Vendor ID (Function 2)24913.2.11 SID–Subsystem ID (Function 2)24913.2.12 INTLN–Interrupt Line Register (Function 2)24913.2.13 INTPN–Interrupt Pin (Function 2)25013.2.14 Miscellaneous Control (Function 2)25013.2.15 SBRNUM–Serial Bus Release Number (Function 2)25013.2.16 LEGSUP–Legacy Support Register (Function 2)25013.2.17 USBREN–USB Resume Enable25213.3 USB Host Controller I/O Space Registers25213.3.1 USBCMD–USB Command Register (I/O)25213.3.2 USBSTS–USB Status Register (I/O)25413.3.3 USBINTR–USB Interrupt Enable Register (I/O)25413.3.4 FRNUM–Frame Number Register (I/O)25513.3.5 FLBASEADD–Frame List Base Address Register (I/O)25513.3.6 SOFMOD–Start of Frame (SOF) Modify Register (I/O)25513.3.7 PORTSC–Port Status and Control Register (I/O)25614 SM Bus Controller Configuration25914.1 SM Bus Configuration Registers (Function 3)25914.2 System Management Register Descriptions26014.2.1 VID–Vendor Identification Register (Function 3)26014.2.2 DID–Device Identification Register (Function 3)26014.2.3 PCICMD–PCI Command Register (Function 3)26014.2.4 PCISTS–PCI Device Status Register (Function 3)26114.2.5 RID–Revision Identification Register (Function 3)26114.2.6 CLASSC–Class Code Register (Function 3)26214.2.7 SMBBA–SMBus Base Address (Function 3)26214.2.8 SVID–Subsystem Vendor ID (Function 3)26214.2.9 SID–Subsystem ID (Function 3)26314.2.10 INTLN–Interrupt Line Register (Function 3)26314.2.11 INTPN–Interrupt Pin (Function 3)26314.2.12 Host Configuration26314.2.13 smbslvc–SMBus Slave Command (Function 3)26414.2.14 smbshdw1–SMBus Slave Shadow Port 1 (Function 3)26414.2.15 smbshdw2–SMBus Slave Shadow Port 2 (Function 3)26414.3 SMBus I/O Space Registers26414.3.1 smbhststs–SMBus Host Status Register (I/O)26514.3.2 smbslvsts–SMBus Slave Status Register (I/O)26514.3.3 smbhstcnt–SMBus Host Control Register (I/O)26614.3.4 smbhstcmd–SMBus Host Command Register (I/O)26714.3.5 smbhstadd–SMBus Host Address Register (I/O)26714.3.6 smbhstdat0–SMBus Host Data 0 Register (I/O)26714.3.7 smbhstdat1–SMBus Host Data 1 Register (I/O)26814.3.8 smbblkdat–SMBus Block Data Register (I/O)26814.3.9 smbslvcnt–SMBus Slave Control Register (I/O)26814.3.10 smbslvdat–SMBus Slave Data Register (I/O)26915 PCI/LPC Bridge Description27115.1 PCI Interface27115.1.1 Transaction Termination27115.1.2 Parity Support27115.1.3 PCI Arbitration27115.2 Interrupt Controller27115.2.1 Programming the Interrupt Controller27215.2.2 End of Interrupt Operation27315.2.3 Modes of Operation27415.2.4 Cascade Mode27515.2.5 Edge and Level Triggered Mode27615.2.6 Interrupt Masks27615.2.7 Reading the Interrupt Controller Status27715.2.8 Interrupt Steering27715.3 Serial Interrupts27815.3.1 Protocol27815.4 Timer/Counters28015.4.1 Programming the Interval Timer28015.5 Real Time Clock28315.5.1 RTC Registers and RAM28415.5.2 RTC Update Cycle28715.5.3 RTC Interrupts28715.5.4 Lockable RAM Ranges28716 IFB Power Management28916.1 Overview28916.2 IFB Power Planes29016.2.1 Power Plane Descriptions29016.2.2 SMI# Generation29016.2.3 SCI Generation29116.2.4 Sleep States29116.2.5 ACPI Bits Not Implemented by IFB29216.2.6 Entry/Exit for the S4 and S5 States29216.3 Handling of Power Failures in IFB293Size: 2.72 MBPages: 294Language: EnglishOpen manual