IBM SA14-2339-04 User Manuals

Table of Contents

• Contents

  5
• Figures

  15
• Tables

  18
• About This Book

  21
  • Who Should Use This Book

    21
  • How to Use This Book

    21
  • Conventions

    22
• Chapter1. Overview

  25
  • 1.1 PPC405 Features

    25
  • 1.2 PowerPC Architecture

    27
  • 1.3 The PPC405 as a PowerPC Implementation

    27
  • 1.4 Processor Core Organization

    28
    • 1.4.1 Instruction and Data Cache Controllers

      28
      • 1.4.1.1 Instruction Cache Unit

        28
      • 1.4.1.2 Data Cache Unit

        29
    • 1.4.2 Memory Management Unit

      29
    • 1.4.3 Timer Facilities

      30
    • 1.4.4 Debug

      31
      • 1.4.4.1 Development Tool Support

        31
      • 1.4.4.2 Debug Modes

        31
    • 1.4.5 Core Interfaces

      31
      • 1.4.5.1 Processor Local Bus

        32
      • 1.4.5.2 Device Control Register Bus

        32
      • 1.4.5.3 Clock and Power Management

        32
      • 1.4.5.4 JTAG

        32
      • 1.4.5.5 Interrupts

        32
      • 1.4.5.6 Auxiliary Processor Unit

        32
      • 1.4.5.7 On-Chip Memory

        32
    • 1.4.6 Data Types

      32
    • 1.4.7 Processor Core Register Set Summary

      33
      • 1.4.7.1 General Purpose Registers

        33
      • 1.4.7.2 Special Purpose Registers

        33
      • 1.4.7.3 Machine State Register

        33
      • 1.4.7.4 Condition Register

        33
      • 1.4.7.5 Device Control Registers

        33
    • 1.4.8 Addressing Modes

      34
• Chapter2. Programming Model

  35
  • 2.1 User and Privileged Programming Models

    35
  • 2.2 Memory Organization and Addressing

    35
    • 2.2.1 Storage Attributes

      36
  • 2.3 Registers

    36
    • 2.3.1 General Purpose Registers (R0-R31)

      39
    • 2.3.2 Special Purpose Registers

      39
      • 2.3.2.1 Count Register (CTR)

        40
      • 2.3.2.2 Link Register (LR)

        41
      • 2.3.2.3 Fixed Point Exception Register (XER)

        41
      • 2.3.2.4 Special Purpose Register General (SPRG0–SPRG7)

        43
      • 2.3.2.5 Processor Version Register (PVR)

        44
    • 2.3.3 Condition Register (CR)

      44
      • 2.3.3.1 CR Fields after Compare Instructions

        45
      • 2.3.3.2 The CR0 Field

        46
    • 2.3.4 The Time Base

      47
    • 2.3.5 Machine State Register (MSR)

      47
    • 2.3.6 Device Control Registers

      49
  • 2.4 Data Types and Alignment

    50
    • 2.4.1 Alignment for Storage Reference and Cache Control Instructions

      50
    • 2.4.2 Alignment and Endian Operation

      51
    • 2.4.3 Summary of Instructions Causing Alignment Exceptions

      51
  • 2.5 Byte Ordering

    51
    • 2.5.1 Structure Mapping Examples

      52
      • 2.5.1.1 Big Endian Mapping

        53
      • 2.5.1.2 Little Endian Mapping

        53
    • 2.5.2 Support for Little Endian Byte Ordering

      53
    • 2.5.3 Endian (E) Storage Attribute

      53
      • 2.5.3.1 Fetching Instructions from Little Endian Storage Regions

        54
      • 2.5.3.2 Accessing Data in Little Endian Storage Regions

        55
      • 2.5.3.3 PowerPC Byte-Reverse Instructions

        55
  • 2.6 Instruction Processing

    57
  • 2.7 Branch Processing

    58
    • 2.7.1 Unconditional Branch Target Addressing Options

      58
    • 2.7.2 Conditional Branch Target Addressing Options

      58
    • 2.7.3 Conditional Branch Condition Register Testing

      59
    • 2.7.4 BO Field on Conditional Branches

      59
    • 2.7.5 Branch Prediction

      60
  • 2.8 Speculative Accesses

    61
    • 2.8.1 Speculative Accesses in the PPC405

      61
      • 2.8.1.1 Prefetch Distance Down an Unresolved Branch Path

        62
      • 2.8.1.2 Prefetch of Branches to the CTR and Branches to the LR

        62
    • 2.8.2 Preventing Inappropriate Speculative Accesses

      62
      • 2.8.2.1 Fetching Past an Interrupt-Causing or Interrupt-Returning Instruction

        62
      • 2.8.2.2 Fetching Past tw or twi Instructions

        63
      • 2.8.2.3 Fetching Past an Unconditional Branch

        63
      • 2.8.2.4 Suggested Locations of Memory-Mapped Hardware

        63
    • 2.8.3 Summary

      64
  • 2.9 Privileged Mode Operation

    64
    • 2.9.1 MSR Bits and Exception Handling

      65
    • 2.9.2 Privileged Instructions

      65
    • 2.9.3 Privileged SPRs

      66
    • 2.9.4 Privileged DCRs

      66
  • 2.10 Synchronization

    67
    • 2.10.1 Context Synchronization

      67
    • 2.10.2 Execution Synchronization

      69
    • 2.10.3 Storage Synchronization

      69
  • 2.11 Instruction Set

    70
    • 2.11.1 Instructions Specific to the IBM PowerPC Embedded Environment

      71
    • 2.11.2 Storage Reference Instructions

      71
    • 2.11.3 Arithmetic Instructions

      72
    • 2.11.4 Logical Instructions

      73
    • 2.11.5 Compare Instructions

      73
    • 2.11.6 Branch Instructions

      74
      • 2.11.6.1 CR Logical Instructions

        74
      • 2.11.6.2 Rotate Instructions

        74
      • 2.11.6.3 Shift Instructions

        75
      • 2.11.6.4 Cache Management Instructions

        75
    • 2.11.7 Interrupt Control Instructions

      75
    • 2.11.8 TLB Management Instructions

      76
    • 2.11.9 Processor Management Instructions

      76
    • 2.11.10 Extended Mnemonics

      76
• Chapter3. Initialization

  79
  • 3.1 Processor State After Reset

    79
    • 3.1.1 Machine State Register Contents after Reset

      80
    • 3.1.2 Contents of Special Purpose Registers after Reset

      81
  • 3.2 PPC405 Initial Processor Sequencing

    81
  • 3.3 Initialization Requirements

    82
  • 3.4 Initialization Code Example

    83
• Chapter4. Cache Operations

  85
  • 4.1 ICU and DCU Organization and Sizes

    86
  • 4.2 ICU Overview

    87
    • 4.2.1 ICU Operations

      88
    • 4.2.2 Instruction Cachability Control

      89
    • 4.2.3 Instruction Cache Synonyms

      89
    • 4.2.4 ICU Coherency

      90
  • 4.3 DCU Overview

    90
    • 4.3.1 DCU Operations

      90
    • 4.3.2 DCU Write Strategies

      91
    • 4.3.3 DCU Load and Store Strategies

      92
    • 4.3.4 Data Cachability Control

      92
    • 4.3.5 DCU Coherency

      93
  • 4.4 Cache Instructions

    93
    • 4.4.1 ICU Instructions

      93
    • 4.4.2 DCU Instructions

      94
  • 4.5 Cache Control and Debugging Features

    95
    • 4.5.1 CCR0 Programming Guidelines

      97
    • 4.5.2 ICU Debugging

      98
    • 4.5.3 DCU Debugging

      99
  • 4.6 DCU Performance

    100
    • 4.6.1 Pipeline Stalls

      100
    • 4.6.2 Cache Operation Priorities

      101
    • 4.6.3 Simultaneous Cache Operations

      101
    • 4.6.4 Sequential Cache Operations

      102
• Chapter5. Fixed-Point Interrupts and Exceptions

  103
  • 5.1 Architectural Definitions and Behavior

    103
  • 5.2 Behavior of the PPC405 Processor Core Implementation

    104
  • 5.3 Interrupt Handling Priorities

    105
  • 5.4 Critical and Noncritical Interrupts

    107
  • 5.5 General Interrupt Handling Registers

    109
    • 5.5.1 Machine State Register (MSR)

      109
    • 5.5.2 Save/Restore Registers 0 and 1 (SRR0–SRR1)

      111
    • 5.5.3 Save/Restore Registers 2 and 3 (SRR2–SRR3)

      111
    • 5.5.4 Exception Vector Prefix Register (EVPR)

      112
    • 5.5.5 Exception Syndrome Register (ESR)

      113
    • 5.5.6 Data Exception Address Register (DEAR)

      115
  • 5.6 Critical Input Interrupts

    115
  • 5.7 Machine Check Interrupts

    116
    • 5.7.1 Instruction Machine Check Handling

      116
    • 5.7.2 Data Machine Check Handling

      117
  • 5.8 Data Storage Interrupt

    118
  • 5.9 Instruction Storage Interrupt

    119
  • 5.10 External Interrupt

    120
    • 5.10.1 External Interrupt Handling

      120
  • 5.11 Alignment Interrupt

    121
  • 5.12 Program Interrupt

    122
  • 5.13 FPU Unavailable Interrupt

    123
  • 5.14 System Call Interrupt

    124
  • 5.15 APU Unavailable Interrupt

    124
  • 5.16 Programmable Interval Timer (PIT) Interrupt

    124
  • 5.17 Fixed Interval Timer (FIT) Interrupt

    125
  • 5.18 Watchdog Timer Interrupt

    126
  • 5.19 Data TLB Miss Interrupt

    127
  • 5.20 Instruction TLB Miss Interrupt

    127
  • 5.21 Debug Interrupt

    128
• Chapter6. Timer Facilities

  129
  • 6.1 Time Base

    129
    • 6.1.1 Reading the Time Base

      131
    • 6.1.2 Writing the Time Base

      131
  • 6.2 Programmable Interval Timer (PIT)

    132
    • 6.2.1 Fixed Interval Timer (FIT)

      133
  • 6.3 Watchdog Timer

    134
  • 6.4 Timer Status Register (TSR)

    136
  • 6.5 Timer Control Register (TCR)

    137
• Chapter7. Memory Management

  139
  • 7.1 MMU Overview

    139
  • 7.2 Address Translation

    139
  • 7.3 Translation Lookaside Buffer (TLB)

    140
    • 7.3.1 Unified TLB

      140
    • 7.3.2 TLB Fields

      141
      • 7.3.2.1 Page Identification Fields

        141
      • 7.3.2.2 Translation Field

        142
      • 7.3.2.3 Access Control Fields

        143
      • 7.3.2.4 Storage Attribute Fields

        143
    • 7.3.3 Shadow Instruction TLB

      144
      • 7.3.3.1 ITLB Accesses

        145
    • 7.3.4 Shadow Data TLB

      145
      • 7.3.4.1 DTLB Accesses

        145
    • 7.3.5 Shadow TLB Consistency

      145
  • 7.4 TLB-Related Interrupts

    147
    • 7.4.1 Data Storage Interrupt

      148
    • 7.4.2 Instruction Storage Interrupt

      148
    • 7.4.3 Data TLB Miss Interrupt

      149
    • 7.4.4 Instruction TLB Miss Interrupt

      149
    • 7.4.5 Program Interrupt

      149
  • 7.5 TLB Management

    149
    • 7.5.1 TLB Search Instructions (tlbsx/tlbsx.)

      150
    • 7.5.2 TLB Read/Write Instructions (tlbre/tlbwe)

      150
    • 7.5.3 TLB Invalidate Instruction (tlbia)

      150
    • 7.5.4 TLB Sync Instruction (tlbsync)

      150
  • 7.6 Recording Page References and Changes

    150
  • 7.7 Access Protection

    151
    • 7.7.1 Access Protection Mechanisms in the TLB

      151
      • 7.7.1.1 General Access Protection

        151
      • 7.7.1.2 Execute Permissions

        152
      • 7.7.1.3 Write Permissions

        152
      • 7.7.1.4 Zone Protection

        152
    • 7.7.2 Access Protection for Cache Control Instructions

      154
    • 7.7.3 Access Protection for String Instructions

      155
  • 7.8 Real-Mode Storage Attribute Control

    155
    • 7.8.1 Storage Attribute Control Registers

      157
      • 7.8.1.1 Data Cache Write-through Register (DCWR)

        157
      • 7.8.1.2 Data Cache Cachability Register (DCCR)

        158
      • 7.8.1.3 Instruction Cache Cachability Register (ICCR)

        158
      • 7.8.1.4 Storage Guarded Register (SGR)

        158
      • 7.8.1.5 Storage User-defined 0 Register (SU0R)

        158
      • 7.8.1.6 Storage Little-Endian Register (SLER)

        158
• Chapter8. Debugging

  159
  • 8.1 Development Tool Support

    159
  • 8.2 Debug Modes

    159
    • 8.2.1 Internal Debug Mode

      159
    • 8.2.2 External Debug Mode

      160
    • 8.2.3 Debug Wait Mode

      160
    • 8.2.4 Real-time Trace Debug Mode

      161
  • 8.3 Processor Control

    161
  • 8.4 Processor Status

    162
  • 8.5 Debug Registers

    162
    • 8.5.1 Debug Control Registers

      162
      • 8.5.1.1 Debug Control Register 0 (DBCR0)

        162
      • 8.5.1.2 Debug Control Register1 (DBCR1)

        164
    • 8.5.2 Debug Status Register (DBSR)

      165
    • 8.5.3 Instruction Address Compare Registers (IAC1–IAC4)

      167
    • 8.5.4 Data Address Compare Registers (DAC1–DAC2)

      167
    • 8.5.5 Data Value Compare Registers (DVC1–DVC2)

      168
    • 8.5.6 Debug Events

      168
    • 8.5.7 Instruction Complete Debug Event

      169
    • 8.5.8 Branch Taken Debug Event

      169
    • 8.5.9 Exception Taken Debug Event

      169
    • 8.5.10 Trap Taken Debug Event

      170
    • 8.5.11 Unconditional Debug Event

      170
    • 8.5.12 IAC Debug Event

      170
      • 8.5.12.1 IAC Exact Address Compare

        170
      • 8.5.12.2 IAC Range Address Compare

        170
    • 8.5.13 DAC Debug Event

      171
      • 8.5.13.1 DAC Exact Address Compare

        171
      • 8.5.13.2 DAC Range Address Compare

        172
      • 8.5.13.3 DAC Applied to Cache Instructions

        173
      • 8.5.13.4 DAC Applied to String Instructions

        174
    • 8.5.14 Data Value Compare Debug Event

      174
    • 8.5.15 Imprecise Debug Event

      177
  • 8.6 Debug Interface

    177
    • 8.6.1 IEEE 1149.1 Test Access Port (JTAG Debug Port)

      177
  • 8.7 JTAG Connector

    178
    • 8.7.1 JTAG Instructions

      179
    • 8.7.2 JTAG Boundary Scan

      179
  • 8.8 Trace Port

    180
• Chapter9. Instruction Set

  181
  • 9.1 Instruction Set Portability

    181
  • 9.2 Instruction Formats

    182
  • 9.3 Pseudocode

    182
    • 9.3.1 Operator Precedence

      185
  • 9.4 Register Usage

    185
  • 9.5 Alphabetical Instruction Listing

    185
    • add

      186
    • addc

      187
    • adde

      188
    • addi

      189
    • addic

      190
    • addic.

      191
    • addis

      192
    • addme

      193
    • addze

      194
    • and

      195
    • andc

      196
    • andi.

      197
    • andis.

      198
    • b

      199
    • bc

      200
    • bcctr

      206
    • bclr

      210
    • cmp

      214
    • cmpi

      215
    • cmpl

      216
    • cmpli

      217
    • cntlzw

      218
    • crand

      219
    • crandc

      220
    • creqv

      221
    • crnand

      222
    • crnor

      223
    • cror

      224
    • crorc

      225
    • crxor

      226
    • dcba

      227
    • dcbf

      229
    • dcbi

      230
    • dcbst

      231
    • dcbt

      232
    • dcbtst

      233
    • dcbz

      234
    • dccci

      236
    • dcread

      237
    • divw

      239
    • divwu

      240
    • eieio

      241
    • eqv

      242
    • extsb

      243
    • extsh

      244
    • icbi

      245
    • icbt

      246
    • iccci

      247
    • icread

      248
    • isync

      250
    • lbz

      251
    • lbzu

      252
    • lbzux

      253
    • lbzx

      254
    • lha

      255
    • lhau

      256
    • lhaux

      257
    • lhax

      258
    • lhbrx

      259
    • lhz

      260
    • lhzu

      261
    • lhzux

      262
    • lhzx

      263
    • lmw

      264
    • lswi

      265
    • lswx

      267
    • lwarx

      269
    • lwbrx

      270
    • lwz

      271
    • lwzu

      272
    • lwzux

      273
    • lwzx

      274
    • macchw

      275
    • macchws

      276
    • macchwsu

      277
    • macchwu

      278
    • machhw

      279
    • machhws

      280
    • machhwsu

      281
    • machhwu

      282
    • maclhw

      283
    • maclhws

      284
    • maclhwsu

      285
    • maclhwu

      286
    • mcrf

      287
    • mcrxr

      288
    • mfcr

      289
    • mfdcr

      290
    • mfmsr

      291
    • mfspr

      292
    • mftb

      294
    • mtcrf

      296
    • mtdcr

      297
    • mtmsr

      298
    • mtspr

      299
    • mulchw

      301
    • mulchwu

      302
    • mulhhw

      303
    • mulhhwu

      304
    • mulhw

      305
    • mulhwu

      306
    • mullhw

      307
    • mullhwu

      308
    • mulli

      309
    • mullw

      310
    • nand

      311
    • neg

      312
    • nmacchw

      313
    • nmacchws

      314
    • nmachhw

      315
    • nmachhws

      316
    • nmaclhw

      317
    • nmaclhws

      318
    • nor

      319
    • or

      320
    • orc

      321
    • ori

      322
    • oris

      323
    • rfci

      324
    • rfi

      325
    • rlwimi

      326
    • rlwinm

      327
    • rlwnm

      330
    • sc

      331
    • slw

      332
    • sraw

      333
    • srawi

      334
    • srw

      335
    • stb

      336
    • stbu

      337
    • stbux

      338
    • stbx

      339
    • sth

      340
    • sthbrx

      341
    • sthu

      342
    • sthux

      343
    • sthx

      344
    • stmw

      345
    • stswi

      346
    • stswx

      347
    • stw

      349
    • stwbrx

      350
    • stwcx.

      351
    • stwu

      353
    • stwux

      354
    • stwx

      355
    • subf

      356
    • subfc

      357
    • subfe

      358
    • subfic

      359
    • subfme

      360
    • subfze

      361
    • sync

      362
    • tlbia

      363
    • tlbre

      364
    • tlbsx

      366
    • tlbsync

      367
    • tlbwe

      368
    • tw

      370
    • twi

      373
    • wrtee

      376
    • wrteei

      377
    • xor

      378
    • xori

      379
    • xoris

      380
• Chapter10. Register Summary

  381
  • 10.1 Reserved Registers

    381
  • 10.2 Reserved Fields

    381
  • 10.3 General Purpose Registers

    381
  • 10.4 Machine State Register and Condition Register

    381
  • 10.5 Special Purpose Registers

    382
  • 10.6 Time Base Registers

    384
  • 10.7 Device Control Registers

    384
  • 10.8 Alphabetical Listing of PPC405 Registers

    385
    • CCR0

      386
    • CR

      388
    • CTR

      389
    • DAC1–DAC2

      390
    • DBCR0

      391
    • DBCR1

      393
    • DBSR

      395
    • DCCR

      397
    • DCWR

      399
    • DEAR

      401
    • DVCR1–DVCR2

      402
    • ESR

      403
    • EVPR

      405
    • GPR0–GPR31

      406
    • IAC1–IAC4

      407
    • ICCR

      408
    • ICDBDR

      410
    • LR

      411
    • MSR

      412
    • PID

      414
    • PIT

      415
    • PVR

      416
    • SGR

      417
    • SLER

      419
    • SPRG0–SPRG7

      421
    • SRR0

      422
    • SRR1

      423
    • SRR2

      424
    • SRR3

      425
    • SU0R

      426
    • TBL

      428
    • TBU

      429
    • TCR

      430
    • TSR

      431
    • USPRG0

      432
    • XER

      433
    • ZPR

      434
• Appendix A. Instruction Summary

  435
  • A.1 Instruction Set and Extended Mnemonics – Alphabetical

    435
  • A.2 Instructions Sorted by Opcode

    467
  • A.3 Instruction Formats

    475
    • A.3.1 Instruction Fields

      475
    • A.3.2 Instruction Format Diagrams

      477
      • A.3.2.1 I-Form

        478
      • A.3.2.2 B-Form

        478
      • A.3.2.3 SC-Form

        478
      • A.3.2.4 D-Form

        478
      • A.3.2.5 X-Form

        479
      • A.3.2.6 XL-Form

        479
      • A.3.2.7 XFX-Form

        480
      • A.3.2.8 X0-Form

        480
      • A.3.2.9 M-Form

        480
• Appendix B. Instructions by Category

  481
  • B.1 Implementation-Specific Instructions

    481
  • B.2 Instructions in the IBM PowerPC Embedded Environment

    485
  • B.3 Privileged Instructions

    487
  • B.4 Assembler Extended Mnemonics

    489
  • B.5 Storage Reference Instructions

    509
  • B.6 Arithmetic and Logical Instructions

    513
  • B.7 Condition Register Logical Instructions

    517
  • B.8 Branch Instructions

    518
  • B.9 Comparison Instructions

    519
  • B.10 Rotate and Shift Instructions

    520
  • B.11 Cache Control Instructions

    521
  • B.12 Interrupt Control Instructions

    522
  • B.13 TLB Management Instructions

    522
  • B.14 Processor Management Instructions

    524
• Appendix C. Code Optimization and Instruction Timings

  527
  • C.1 Code Optimization Guidelines

    527
    • C.1.1 Condition Register Bits for Boolean Variables

      527
    • C.1.2 CR Logical Instruction for Compound Branches

      527
    • C.1.3 Floating-Point Emulation

      527
    • C.1.4 Cache Usage

      528
    • C.1.5 CR Dependencies

      528
    • C.1.6 Branch Prediction

      528
    • C.1.7 Alignment

      528
  • C.2 Instruction Timings

    529
    • C.2.1 General Rules

      529
    • C.2.2 Branches

      529
    • C.2.3 Multiplies

      530
    • C.2.4 Scalar Load Instructions

      531
    • C.2.5 Scalar Store Instructions

      532
    • C.2.6 Alignment in Scalar Load and Store Instructions

      532
    • C.2.7 String and Multiple Instructions

      532
    • C.2.8 Loads and Store Misses

      533
    • C.2.9 Instruction Cache Misses

      533
• Index

  535