User Manual (46M1081)Table of Contents1 Introduction151.1 Terminology151.1.1 Processor Terminology151.2 References172 Register Description192.1 Register Terminology192.2 Platform Configuration Structure202.3 Device Mapping212.4 Detailed Configuration Space Maps232.5 PCI Standard Registers452.5.1 VID - Vendor Identification Register452.5.2 DID - Device Identification Register452.5.3 RID - Revision Identification Register462.5.4 CCR - Class Code Register462.5.5 HDR - Header Type Register472.5.6 SID/SVID - Subsystem Identity/Subsystem Vendor Identification Register472.5.7 PCICMD - Command Register482.5.8 PCISTS - PCI Status Register492.6 Generic Non-core Registers502.6.1 MAXREQUEST_LC502.6.2 MAXREQUEST_LS512.6.3 MAXREQUEST_LL512.6.4 MAX_RTIDS512.6.5 DESIRED_CORES522.6.6 MEMLOCK_STATUS522.6.7 MC_CFG_CONTROL532.6.8 POWER_CNTRL_ERR_STATUS532.6.9 CURRENT_UCLK_RATIO542.6.10 MIRROR_PORT_CTL552.6.11 MIP_PH_CTR_L0 MIP_PH_CTR_L1552.6.12 MIP_PH_PRT_L0 MIP_PH_PRT_L1562.7 SAD - System Address Decoder Registers562.7.1 SAD_PAM0123562.7.2 SAD_PAM456582.7.3 SAD_HEN592.7.4 SAD_SMRAM592.7.5 SAD_PCIEXBAR602.7.6 SAD_DRAM_RULE_0 SAD_DRAM_RULE_1 SAD_DRAM_RULE_2 SAD_DRAM_RULE_3 SAD_DRAM_RULE_4 SAD_DRAM_RULE_5 SAD_DRAM_RULE_6 SAD_DRAM_RULE_7602.7.7 SAD_INTERLEAVE_LIST_0 SAD_INTERLEAVE_LIST_1 SAD_INTERLEAVE_LIST_2 SAD_INTERLEAVE_LIST_3 SAD_INTERLEAVE_LIST_4 SAD_INTERLEAVE_LIST_5 SAD_INTERLEAVE_LIST_6 SAD_INTERLEAVE_LIST_7612.8 Intel QPI Link Registers612.8.1 QPI_QPILCP_L0 QPI_QPILCP_L1612.8.2 QPI_QPILCL_L0 QPI_QPILCL_L1622.8.3 QPI_QPILS_L0 QPI_QPILS_L1632.8.4 QPI_DEF_RMT_VN_CREDITS_L0 QPI_DEF_RMT_VN_CREDITS_L1632.8.5 QPI_RMT_QPILP0_STAT_L0 QPI_RMT_QPILP0_STAT_L1632.8.6 QPI_RMT_QPILP1_STAT_L0 QPI_RMT_QPILP1_STAT_L1642.8.7 QPI_RMT_QPILP2_STAT_L0 QPI_RMT_QPILP2_STAT_L1642.8.8 QPI_RMT_QPILP3_STAT_L0 QPI_RMT_QPILP3_STAT_L1652.9 Intel QPI Physical Layer Registers662.9.1 QPI_0_PH_CPR QPI_1_PH_CPR662.9.2 QPI_0_PH_CTR QPI_1_PH_CTR672.9.3 QPI_0_PH_PIS QPI_1_PH_PIS682.9.4 QPI_0_PH_PTV QPI_1_PH_PTV692.9.5 QPI_0_PH_LDC QPI_1_PH_LDC692.9.6 QPI_0_PH_PRT QPI_1_PH_PRT702.9.7 QPI_0_PH_PMR0 QPI_1_PH_PMR0702.9.8 QPI_0_EP_SR QPI_1_EP_SR712.9.9 QPI_0_EP_MCTR QPI_1_EP_MCTR712.10 Intel QPI Miscellaneous Registers722.10.1 QPI_0_PLL_STATUS QPI_1_PLL_STATUS722.10.2 QPI_0_PLL_RATIO QPI_1_PLL_RATIO722.11 Integrated Memory Controller Control Registers732.11.1 MC_CONTROL732.11.2 MC_STATUS742.11.3 MC_SMI_DIMM_ERROR_STATUS742.11.4 MC_SMI_CNTRL752.11.5 MC_RESET_CONTROL762.11.6 MC_CHANNEL_MAPPER762.11.7 MC_MAX_DOD772.11.8 MC_RD_CRDT_INIT772.11.9 MC_CRDT_WR_THLD782.11.10 MC_SCRUBADDR_LO792.11.11 MC_SCRUBADDR_HI792.12 TAD - Target Address Decoder Registers802.12.1 TAD_DRAM_RULE_0 TAD_DRAM_RULE_1 TAD_DRAM_RULE_2 TAD_DRAM_RULE_3 TAD_DRAM_RULE_4 TAD_DRAM_RULE_5 TAD_DRAM_RULE_6 TAD_DRAM_RULE_7802.12.2 TAD_INTERLEAVE_LIST_0 TAD_INTERLEAVE_LIST_1 TAD_INTERLEAVE_LIST_2 TAD_INTERLEAVE_LIST_3 TAD_INTERLEAVE_LIST_4 TAD_INTERLEAVE_LIST_5 TAD_INTERLEAVE_LIST_6 TAD_INTERLEAVE_LIST_7812.13 Integrated Memory Controller RAS Registers822.13.1 MC_SSRCONTROL822.13.2 MC_SCRUB_CONTROL832.13.3 MC_RAS_ENABLES832.13.4 MC_RAS_STATUS832.13.5 MC_SSRSTATUS842.13.6 MC_COR_ECC_CNT_0 MC_COR_ECC_CNT_1 MC_COR_ECC_CNT_2 MC_COR_ECC_CNT_3 MC_COR_ECC_CNT_4 MC_COR_ECC_CNT_5842.14 Integrated Memory Controller Test Registers852.14.1 MC_TEST_ERR_RCV1852.14.2 MC_TEST_ERR_RCV0852.14.3 MC_TEST_PH_CTR862.14.4 MC_TEST_PH_PIS862.14.5 MC_TEST_PAT_GCTR862.14.6 MC_TEST_PAT_BA872.14.7 MC_TEST_PAT_IS872.14.8 MC_TEST_PAT_DCD872.15 Integrated Memory Controller Channel Control Registers882.15.1 MC_CHANNEL_0_DIMM_RESET_CMD MC_CHANNEL_1_DIMM_RESET_CMD MC_CHANNEL_2_DIMM_RESET_CMD882.15.2 MC_CHANNEL_0_DIMM_INIT_CMD MC_CHANNEL_1_DIMM_INIT_CMD MC_CHANNEL_2_DIMM_INIT_CMD882.15.3 MC_CHANNEL_0_DIMM_INIT_PARAMS MC_CHANNEL_1_DIMM_INIT_PARAMS MC_CHANNEL_2_DIMM_INIT_PARAMS892.15.4 MC_CHANNEL_0_DIMM_INIT_STATUS MC_CHANNEL_1_DIMM_INIT_STATUS MC_CHANNEL_2_DIMM_INIT_STATUS912.15.5 MC_CHANNEL_0_DDR3CMD MC_CHANNEL_1_DDR3CMD MC_CHANNEL_2_DDR3CMD922.15.6 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT932.15.7 MC_CHANNEL_0_MRS_VALUE_0_1 MC_CHANNEL_1_MRS_VALUE_0_1 MC_CHANNEL_2_MRS_VALUE_0_1932.15.8 MC_CHANNEL_0_MRS_VALUE_2 MC_CHANNEL_1_MRS_VALUE_2 MC_CHANNEL_2_MRS_VALUE_2942.15.9 MC_CHANNEL_0_RANK_PRESENT MC_CHANNEL_1_RANK_PRESENT MC_CHANNEL_2_RANK_PRESENT942.15.10 MC_CHANNEL_0_RANK_TIMING_A MC_CHANNEL_1_RANK_TIMING_A MC_CHANNEL_2_RANK_TIMING_A952.15.11 MC_CHANNEL_0_RANK_TIMING_B MC_CHANNEL_1_RANK_TIMING_B MC_CHANNEL_2_RANK_TIMING_B982.15.12 MC_CHANNEL_0_BANK_TIMING MC_CHANNEL_1_BANK_TIMING MC_CHANNEL_2_BANK_TIMING992.15.13 MC_CHANNEL_0_REFRESH_TIMING MC_CHANNEL_1_REFRESH_TIMING MC_CHANNEL_2_REFRESH_TIMING992.15.14 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING MC_CHANNEL_2_CKE_TIMING1002.15.15 MC_CHANNEL_0_ZQ_TIMING MC_CHANNEL_1_ZQ_TIMING MC_CHANNEL_2_ZQ_TIMING1002.15.16 MC_CHANNEL_0_RCOMP_PARAMS MC_CHANNEL_1_RCOMP_PARAMS MC_CHANNEL_2_RCOMP_PARAMS1012.15.17 MC_CHANNEL_0_ODT_PARAMS1 MC_CHANNEL_1_ODT_PARAMS1 MC_CHANNEL_2_ODT_PARAMS11012.15.18 MC_CHANNEL_0_ODT_PARAMS2 MC_CHANNEL_1_ODT_PARAMS2 MC_CHANNEL_2_ODT_PARAMS21022.15.19 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_RD1022.15.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_RD1032.15.21 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_WR1032.15.22 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_WR1032.15.23 MC_CHANNEL_0_WAQ_PARAMS MC_CHANNEL_1_WAQ_PARAMS MC_CHANNEL_2_WAQ_PARAMS1042.15.24 MC_CHANNEL_0_SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULER_PARAMS MC_CHANNEL_2_SCHEDULER_PARAMS1042.15.25 MC_CHANNEL_0_MAINTENANCE_OPS MC_CHANNEL_1_MAINTENANCE_OPS MC_CHANNEL_2_MAINTENANCE_OPS1052.15.26 MC_CHANNEL_0_TX_BG_SETTINGS MC_CHANNEL_1_TX_BG_SETTINGS MC_CHANNEL_2_TX_BG_SETTINGS1052.15.27 MC_CHANNEL_0_RX_BGF_SETTINGS MC_CHANNEL_1_RX_BGF_SETTINGS MC_CHANNEL_2_RX_BGF_SETTINGS1062.15.28 MC_CHANNEL_0_EW_BGF_SETTINGS MC_CHANNEL_1_EW_BGF_SETTINGS MC_CHANNEL_2_EW_BGF_SETTINGS1062.15.29 MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_2_EW_BGF_OFFSET_SETTINGS1062.15.30 MC_CHANNEL_0_ROUND_TRIP_LATENCY MC_CHANNEL_1_ROUND_TRIP_LATENCY MC_CHANNEL_2_ROUND_TRIP_LATENCY1072.15.31 MC_CHANNEL_0_PAGETABLE_PARAMS1 MC_CHANNEL_1_PAGETABLE_PARAMS1 MC_CHANNEL_2_PAGETABLE_PARAMS11072.15.32 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH21072.15.33 MC_TX_BG_CMD_OFFSET_SETTINGS_CH0 MC_TX_BG_CMD_OFFSET_SETTINGS_CH1 MC_TX_BG_CMD_OFFSET_SETTINGS_CH21082.15.34 MC_TX_BG_DATA_OFFSET_SETTINGS_CH0 MC_TX_BG_DATA_OFFSET_SETTINGS_CH1 MC_TX_BG_DATA_OFFSET_SETTINGS_CH21082.16 Integrated Memory Controller Channel Address Registers1092.16.1 MC_DOD_CH0_0 MC_DOD_CH0_1 MC_DOD_CH0_21092.16.2 MC_DOD_CH1_0 MC_DOD_CH1_1 MC_DOD_CH1_21102.16.3 MC_DOD_CH2_0 MC_DOD_CH2_1 MC_DOD_CH2_21112.16.4 MC_SAG_CH0_0 MC_SAG_CH0_1 MC_SAG_CH0_2 MC_SAG_CH0_3 MC_SAG_CH0_4 MC_SAG_CH0_5 MC_SAG_CH0_6 MC_SAG_CH0_7 MC_SAG_CH1_0 MC_S...1122.17 Integrated Memory Controller Channel Rank Registers1132.17.1 MC_RIR_LIMIT_CH0_0 MC_RIR_LIMIT_CH0_1 MC_RIR_LIMIT_CH0_2 MC_RIR_LIMIT_CH0_3 MC_RIR_LIMIT_CH0_4 MC_RIR_LIMIT_CH0_5 MC_RIR_...1132.17.2 MC_RIR_WAY_CH0_0 MC_RIR_WAY_CH0_1 MC_RIR_WAY_CH0_2 MC_RIR_WAY_CH0_3 MC_RIR_WAY_CH0_4 MC_RIR_WAY_CH0_5 MC_RIR_WAY_CH0_6 MC...1142.17.3 MC_RIR_WAY_CH1_0 MC_RIR_WAY_CH1_1 MC_RIR_WAY_CH1_2 MC_RIR_WAY_CH1_3 MC_RIR_WAY_CH1_4 MC_RIR_WAY_CH1_5 MC_RIR_WAY_CH1_6 MC...1152.17.4 MC_RIR_WAY_CH2_0 MC_RIR_WAY_CH2_1 MC_RIR_WAY_CH2_2 MC_RIR_WAY_CH2_3 MC_RIR_WAY_CH2_4 MC_RIR_WAY_CH2_5 MC_RIR_WAY_CH2_6 MC...1172.18 Memory Thermal Control1182.18.1 MC_THERMAL_CONTROL0 MC_THERMAL_CONTROL1 MC_THERMAL_CONTROL21182.18.2 MC_THERMAL_STATUS0 MC_THERMAL_STATUS1 MC_THERMAL_STATUS21192.18.3 MC_THERMAL_DEFEATURE0 MC_THERMAL_DEFEATURE1 MC_THERMAL_DEFEATURE21192.18.4 MC_THERMAL_PARAMS_A0 MC_THERMAL_PARAMS_A1 MC_THERMAL_PARAMS_A21192.18.5 MC_THERMAL_PARAMS_B0 MC_THERMAL_PARAMS_B1 MC_THERMAL_PARAMS_B21202.18.6 MC_COOLING_COEF0 MC_COOLING_COEF1 MC_COOLING_COEF21202.18.7 MC_CLOSED_LOOP0 MC_CLOSED_LOOP1 MC_CLOSED_LOOP21212.18.8 MC_THROTTLE_OFFSET0 MC_THROTTLE_OFFSET1 MC_THROTTLE_OFFSET21212.18.9 MC_RANK_VIRTUAL_TEMP0 MC_RANK_VIRTUAL_TEMP1 MC_RANK_VIRTUAL_TEMP21222.18.10 MC_DDR_THERM_COMMAND0 MC_DDR_THERM_COMMAND1 MC_DDR_THERM_COMMAND21222.18.11 MC_DDR_THERM_STATUS0 MC_DDR_THERM_STATUS1 MC_DDR_THERM_STATUS21232.19 Integrated Memory Controller Miscellaneous Registers1232.19.1 MC_DIMM_CLK_RATIO_STATUS1232.19.2 MC_DIMM_CLK_RATIO1243 DIMM Population Requirements1253.1 General Population Requirements1253.2 Populating DIMMs Within a Channel1263.2.1 DIMM Population for Three Slots per Channel1263.2.2 DIMM Population for Two Slots per Channel128Size: 1.88 MBPages: 130Language: EnglishOpen manual
User Manual (44T1736)Table of Contents1 Introduction151.1 Terminology151.1.1 Processor Terminology151.2 References172 Register Description192.1 Register Terminology192.2 Platform Configuration Structure202.3 Device Mapping212.4 Detailed Configuration Space Maps232.5 PCI Standard Registers452.5.1 VID - Vendor Identification Register452.5.2 DID - Device Identification Register452.5.3 RID - Revision Identification Register462.5.4 CCR - Class Code Register462.5.5 HDR - Header Type Register472.5.6 SID/SVID - Subsystem Identity/Subsystem Vendor Identification Register472.5.7 PCICMD - Command Register482.5.8 PCISTS - PCI Status Register492.6 Generic Non-core Registers502.6.1 MAXREQUEST_LC502.6.2 MAXREQUEST_LS512.6.3 MAXREQUEST_LL512.6.4 MAX_RTIDS512.6.5 DESIRED_CORES522.6.6 MEMLOCK_STATUS522.6.7 MC_CFG_CONTROL532.6.8 POWER_CNTRL_ERR_STATUS532.6.9 CURRENT_UCLK_RATIO542.6.10 MIRROR_PORT_CTL552.6.11 MIP_PH_CTR_L0 MIP_PH_CTR_L1552.6.12 MIP_PH_PRT_L0 MIP_PH_PRT_L1562.7 SAD - System Address Decoder Registers562.7.1 SAD_PAM0123562.7.2 SAD_PAM456582.7.3 SAD_HEN592.7.4 SAD_SMRAM592.7.5 SAD_PCIEXBAR602.7.6 SAD_DRAM_RULE_0 SAD_DRAM_RULE_1 SAD_DRAM_RULE_2 SAD_DRAM_RULE_3 SAD_DRAM_RULE_4 SAD_DRAM_RULE_5 SAD_DRAM_RULE_6 SAD_DRAM_RULE_7602.7.7 SAD_INTERLEAVE_LIST_0 SAD_INTERLEAVE_LIST_1 SAD_INTERLEAVE_LIST_2 SAD_INTERLEAVE_LIST_3 SAD_INTERLEAVE_LIST_4 SAD_INTERLEAVE_LIST_5 SAD_INTERLEAVE_LIST_6 SAD_INTERLEAVE_LIST_7612.8 Intel QPI Link Registers612.8.1 QPI_QPILCP_L0 QPI_QPILCP_L1612.8.2 QPI_QPILCL_L0 QPI_QPILCL_L1622.8.3 QPI_QPILS_L0 QPI_QPILS_L1632.8.4 QPI_DEF_RMT_VN_CREDITS_L0 QPI_DEF_RMT_VN_CREDITS_L1632.8.5 QPI_RMT_QPILP0_STAT_L0 QPI_RMT_QPILP0_STAT_L1632.8.6 QPI_RMT_QPILP1_STAT_L0 QPI_RMT_QPILP1_STAT_L1642.8.7 QPI_RMT_QPILP2_STAT_L0 QPI_RMT_QPILP2_STAT_L1642.8.8 QPI_RMT_QPILP3_STAT_L0 QPI_RMT_QPILP3_STAT_L1652.9 Intel QPI Physical Layer Registers662.9.1 QPI_0_PH_CPR QPI_1_PH_CPR662.9.2 QPI_0_PH_CTR QPI_1_PH_CTR672.9.3 QPI_0_PH_PIS QPI_1_PH_PIS682.9.4 QPI_0_PH_PTV QPI_1_PH_PTV692.9.5 QPI_0_PH_LDC QPI_1_PH_LDC692.9.6 QPI_0_PH_PRT QPI_1_PH_PRT702.9.7 QPI_0_PH_PMR0 QPI_1_PH_PMR0702.9.8 QPI_0_EP_SR QPI_1_EP_SR712.9.9 QPI_0_EP_MCTR QPI_1_EP_MCTR712.10 Intel QPI Miscellaneous Registers722.10.1 QPI_0_PLL_STATUS QPI_1_PLL_STATUS722.10.2 QPI_0_PLL_RATIO QPI_1_PLL_RATIO722.11 Integrated Memory Controller Control Registers732.11.1 MC_CONTROL732.11.2 MC_STATUS742.11.3 MC_SMI_DIMM_ERROR_STATUS742.11.4 MC_SMI_CNTRL752.11.5 MC_RESET_CONTROL762.11.6 MC_CHANNEL_MAPPER762.11.7 MC_MAX_DOD772.11.8 MC_RD_CRDT_INIT772.11.9 MC_CRDT_WR_THLD782.11.10 MC_SCRUBADDR_LO792.11.11 MC_SCRUBADDR_HI792.12 TAD - Target Address Decoder Registers802.12.1 TAD_DRAM_RULE_0 TAD_DRAM_RULE_1 TAD_DRAM_RULE_2 TAD_DRAM_RULE_3 TAD_DRAM_RULE_4 TAD_DRAM_RULE_5 TAD_DRAM_RULE_6 TAD_DRAM_RULE_7802.12.2 TAD_INTERLEAVE_LIST_0 TAD_INTERLEAVE_LIST_1 TAD_INTERLEAVE_LIST_2 TAD_INTERLEAVE_LIST_3 TAD_INTERLEAVE_LIST_4 TAD_INTERLEAVE_LIST_5 TAD_INTERLEAVE_LIST_6 TAD_INTERLEAVE_LIST_7812.13 Integrated Memory Controller RAS Registers822.13.1 MC_SSRCONTROL822.13.2 MC_SCRUB_CONTROL832.13.3 MC_RAS_ENABLES832.13.4 MC_RAS_STATUS832.13.5 MC_SSRSTATUS842.13.6 MC_COR_ECC_CNT_0 MC_COR_ECC_CNT_1 MC_COR_ECC_CNT_2 MC_COR_ECC_CNT_3 MC_COR_ECC_CNT_4 MC_COR_ECC_CNT_5842.14 Integrated Memory Controller Test Registers852.14.1 MC_TEST_ERR_RCV1852.14.2 MC_TEST_ERR_RCV0852.14.3 MC_TEST_PH_CTR862.14.4 MC_TEST_PH_PIS862.14.5 MC_TEST_PAT_GCTR862.14.6 MC_TEST_PAT_BA872.14.7 MC_TEST_PAT_IS872.14.8 MC_TEST_PAT_DCD872.15 Integrated Memory Controller Channel Control Registers882.15.1 MC_CHANNEL_0_DIMM_RESET_CMD MC_CHANNEL_1_DIMM_RESET_CMD MC_CHANNEL_2_DIMM_RESET_CMD882.15.2 MC_CHANNEL_0_DIMM_INIT_CMD MC_CHANNEL_1_DIMM_INIT_CMD MC_CHANNEL_2_DIMM_INIT_CMD882.15.3 MC_CHANNEL_0_DIMM_INIT_PARAMS MC_CHANNEL_1_DIMM_INIT_PARAMS MC_CHANNEL_2_DIMM_INIT_PARAMS892.15.4 MC_CHANNEL_0_DIMM_INIT_STATUS MC_CHANNEL_1_DIMM_INIT_STATUS MC_CHANNEL_2_DIMM_INIT_STATUS912.15.5 MC_CHANNEL_0_DDR3CMD MC_CHANNEL_1_DDR3CMD MC_CHANNEL_2_DDR3CMD922.15.6 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT932.15.7 MC_CHANNEL_0_MRS_VALUE_0_1 MC_CHANNEL_1_MRS_VALUE_0_1 MC_CHANNEL_2_MRS_VALUE_0_1932.15.8 MC_CHANNEL_0_MRS_VALUE_2 MC_CHANNEL_1_MRS_VALUE_2 MC_CHANNEL_2_MRS_VALUE_2942.15.9 MC_CHANNEL_0_RANK_PRESENT MC_CHANNEL_1_RANK_PRESENT MC_CHANNEL_2_RANK_PRESENT942.15.10 MC_CHANNEL_0_RANK_TIMING_A MC_CHANNEL_1_RANK_TIMING_A MC_CHANNEL_2_RANK_TIMING_A952.15.11 MC_CHANNEL_0_RANK_TIMING_B MC_CHANNEL_1_RANK_TIMING_B MC_CHANNEL_2_RANK_TIMING_B982.15.12 MC_CHANNEL_0_BANK_TIMING MC_CHANNEL_1_BANK_TIMING MC_CHANNEL_2_BANK_TIMING992.15.13 MC_CHANNEL_0_REFRESH_TIMING MC_CHANNEL_1_REFRESH_TIMING MC_CHANNEL_2_REFRESH_TIMING992.15.14 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING MC_CHANNEL_2_CKE_TIMING1002.15.15 MC_CHANNEL_0_ZQ_TIMING MC_CHANNEL_1_ZQ_TIMING MC_CHANNEL_2_ZQ_TIMING1002.15.16 MC_CHANNEL_0_RCOMP_PARAMS MC_CHANNEL_1_RCOMP_PARAMS MC_CHANNEL_2_RCOMP_PARAMS1012.15.17 MC_CHANNEL_0_ODT_PARAMS1 MC_CHANNEL_1_ODT_PARAMS1 MC_CHANNEL_2_ODT_PARAMS11012.15.18 MC_CHANNEL_0_ODT_PARAMS2 MC_CHANNEL_1_ODT_PARAMS2 MC_CHANNEL_2_ODT_PARAMS21022.15.19 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_RD1022.15.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_RD1032.15.21 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_WR1032.15.22 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_WR1032.15.23 MC_CHANNEL_0_WAQ_PARAMS MC_CHANNEL_1_WAQ_PARAMS MC_CHANNEL_2_WAQ_PARAMS1042.15.24 MC_CHANNEL_0_SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULER_PARAMS MC_CHANNEL_2_SCHEDULER_PARAMS1042.15.25 MC_CHANNEL_0_MAINTENANCE_OPS MC_CHANNEL_1_MAINTENANCE_OPS MC_CHANNEL_2_MAINTENANCE_OPS1052.15.26 MC_CHANNEL_0_TX_BG_SETTINGS MC_CHANNEL_1_TX_BG_SETTINGS MC_CHANNEL_2_TX_BG_SETTINGS1052.15.27 MC_CHANNEL_0_RX_BGF_SETTINGS MC_CHANNEL_1_RX_BGF_SETTINGS MC_CHANNEL_2_RX_BGF_SETTINGS1062.15.28 MC_CHANNEL_0_EW_BGF_SETTINGS MC_CHANNEL_1_EW_BGF_SETTINGS MC_CHANNEL_2_EW_BGF_SETTINGS1062.15.29 MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_2_EW_BGF_OFFSET_SETTINGS1062.15.30 MC_CHANNEL_0_ROUND_TRIP_LATENCY MC_CHANNEL_1_ROUND_TRIP_LATENCY MC_CHANNEL_2_ROUND_TRIP_LATENCY1072.15.31 MC_CHANNEL_0_PAGETABLE_PARAMS1 MC_CHANNEL_1_PAGETABLE_PARAMS1 MC_CHANNEL_2_PAGETABLE_PARAMS11072.15.32 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH21072.15.33 MC_TX_BG_CMD_OFFSET_SETTINGS_CH0 MC_TX_BG_CMD_OFFSET_SETTINGS_CH1 MC_TX_BG_CMD_OFFSET_SETTINGS_CH21082.15.34 MC_TX_BG_DATA_OFFSET_SETTINGS_CH0 MC_TX_BG_DATA_OFFSET_SETTINGS_CH1 MC_TX_BG_DATA_OFFSET_SETTINGS_CH21082.16 Integrated Memory Controller Channel Address Registers1092.16.1 MC_DOD_CH0_0 MC_DOD_CH0_1 MC_DOD_CH0_21092.16.2 MC_DOD_CH1_0 MC_DOD_CH1_1 MC_DOD_CH1_21102.16.3 MC_DOD_CH2_0 MC_DOD_CH2_1 MC_DOD_CH2_21112.16.4 MC_SAG_CH0_0 MC_SAG_CH0_1 MC_SAG_CH0_2 MC_SAG_CH0_3 MC_SAG_CH0_4 MC_SAG_CH0_5 MC_SAG_CH0_6 MC_SAG_CH0_7 MC_SAG_CH1_0 MC_S...1122.17 Integrated Memory Controller Channel Rank Registers1132.17.1 MC_RIR_LIMIT_CH0_0 MC_RIR_LIMIT_CH0_1 MC_RIR_LIMIT_CH0_2 MC_RIR_LIMIT_CH0_3 MC_RIR_LIMIT_CH0_4 MC_RIR_LIMIT_CH0_5 MC_RIR_...1132.17.2 MC_RIR_WAY_CH0_0 MC_RIR_WAY_CH0_1 MC_RIR_WAY_CH0_2 MC_RIR_WAY_CH0_3 MC_RIR_WAY_CH0_4 MC_RIR_WAY_CH0_5 MC_RIR_WAY_CH0_6 MC...1142.17.3 MC_RIR_WAY_CH1_0 MC_RIR_WAY_CH1_1 MC_RIR_WAY_CH1_2 MC_RIR_WAY_CH1_3 MC_RIR_WAY_CH1_4 MC_RIR_WAY_CH1_5 MC_RIR_WAY_CH1_6 MC...1152.17.4 MC_RIR_WAY_CH2_0 MC_RIR_WAY_CH2_1 MC_RIR_WAY_CH2_2 MC_RIR_WAY_CH2_3 MC_RIR_WAY_CH2_4 MC_RIR_WAY_CH2_5 MC_RIR_WAY_CH2_6 MC...1172.18 Memory Thermal Control1182.18.1 MC_THERMAL_CONTROL0 MC_THERMAL_CONTROL1 MC_THERMAL_CONTROL21182.18.2 MC_THERMAL_STATUS0 MC_THERMAL_STATUS1 MC_THERMAL_STATUS21192.18.3 MC_THERMAL_DEFEATURE0 MC_THERMAL_DEFEATURE1 MC_THERMAL_DEFEATURE21192.18.4 MC_THERMAL_PARAMS_A0 MC_THERMAL_PARAMS_A1 MC_THERMAL_PARAMS_A21192.18.5 MC_THERMAL_PARAMS_B0 MC_THERMAL_PARAMS_B1 MC_THERMAL_PARAMS_B21202.18.6 MC_COOLING_COEF0 MC_COOLING_COEF1 MC_COOLING_COEF21202.18.7 MC_CLOSED_LOOP0 MC_CLOSED_LOOP1 MC_CLOSED_LOOP21212.18.8 MC_THROTTLE_OFFSET0 MC_THROTTLE_OFFSET1 MC_THROTTLE_OFFSET21212.18.9 MC_RANK_VIRTUAL_TEMP0 MC_RANK_VIRTUAL_TEMP1 MC_RANK_VIRTUAL_TEMP21222.18.10 MC_DDR_THERM_COMMAND0 MC_DDR_THERM_COMMAND1 MC_DDR_THERM_COMMAND21222.18.11 MC_DDR_THERM_STATUS0 MC_DDR_THERM_STATUS1 MC_DDR_THERM_STATUS21232.19 Integrated Memory Controller Miscellaneous Registers1232.19.1 MC_DIMM_CLK_RATIO_STATUS1232.19.2 MC_DIMM_CLK_RATIO1243 DIMM Population Requirements1253.1 General Population Requirements1253.2 Populating DIMMs Within a Channel1263.2.1 DIMM Population for Three Slots per Channel1263.2.2 DIMM Population for Two Slots per Channel128Size: 1.88 MBPages: 130Language: EnglishOpen manual
User Manual (46D1352)Table of Contents1 Introduction151.1 Terminology151.1.1 Processor Terminology151.2 References172 Register Description192.1 Register Terminology192.2 Platform Configuration Structure202.3 Device Mapping212.4 Detailed Configuration Space Maps232.5 PCI Standard Registers452.5.1 VID - Vendor Identification Register452.5.2 DID - Device Identification Register452.5.3 RID - Revision Identification Register462.5.4 CCR - Class Code Register462.5.5 HDR - Header Type Register472.5.6 SID/SVID - Subsystem Identity/Subsystem Vendor Identification Register472.5.7 PCICMD - Command Register482.5.8 PCISTS - PCI Status Register492.6 Generic Non-core Registers502.6.1 MAXREQUEST_LC502.6.2 MAXREQUEST_LS512.6.3 MAXREQUEST_LL512.6.4 MAX_RTIDS512.6.5 DESIRED_CORES522.6.6 MEMLOCK_STATUS522.6.7 MC_CFG_CONTROL532.6.8 POWER_CNTRL_ERR_STATUS532.6.9 CURRENT_UCLK_RATIO542.6.10 MIRROR_PORT_CTL552.6.11 MIP_PH_CTR_L0 MIP_PH_CTR_L1552.6.12 MIP_PH_PRT_L0 MIP_PH_PRT_L1562.7 SAD - System Address Decoder Registers562.7.1 SAD_PAM0123562.7.2 SAD_PAM456582.7.3 SAD_HEN592.7.4 SAD_SMRAM592.7.5 SAD_PCIEXBAR602.7.6 SAD_DRAM_RULE_0 SAD_DRAM_RULE_1 SAD_DRAM_RULE_2 SAD_DRAM_RULE_3 SAD_DRAM_RULE_4 SAD_DRAM_RULE_5 SAD_DRAM_RULE_6 SAD_DRAM_RULE_7602.7.7 SAD_INTERLEAVE_LIST_0 SAD_INTERLEAVE_LIST_1 SAD_INTERLEAVE_LIST_2 SAD_INTERLEAVE_LIST_3 SAD_INTERLEAVE_LIST_4 SAD_INTERLEAVE_LIST_5 SAD_INTERLEAVE_LIST_6 SAD_INTERLEAVE_LIST_7612.8 Intel QPI Link Registers612.8.1 QPI_QPILCP_L0 QPI_QPILCP_L1612.8.2 QPI_QPILCL_L0 QPI_QPILCL_L1622.8.3 QPI_QPILS_L0 QPI_QPILS_L1632.8.4 QPI_DEF_RMT_VN_CREDITS_L0 QPI_DEF_RMT_VN_CREDITS_L1632.8.5 QPI_RMT_QPILP0_STAT_L0 QPI_RMT_QPILP0_STAT_L1632.8.6 QPI_RMT_QPILP1_STAT_L0 QPI_RMT_QPILP1_STAT_L1642.8.7 QPI_RMT_QPILP2_STAT_L0 QPI_RMT_QPILP2_STAT_L1642.8.8 QPI_RMT_QPILP3_STAT_L0 QPI_RMT_QPILP3_STAT_L1652.9 Intel QPI Physical Layer Registers662.9.1 QPI_0_PH_CPR QPI_1_PH_CPR662.9.2 QPI_0_PH_CTR QPI_1_PH_CTR672.9.3 QPI_0_PH_PIS QPI_1_PH_PIS682.9.4 QPI_0_PH_PTV QPI_1_PH_PTV692.9.5 QPI_0_PH_LDC QPI_1_PH_LDC692.9.6 QPI_0_PH_PRT QPI_1_PH_PRT702.9.7 QPI_0_PH_PMR0 QPI_1_PH_PMR0702.9.8 QPI_0_EP_SR QPI_1_EP_SR712.9.9 QPI_0_EP_MCTR QPI_1_EP_MCTR712.10 Intel QPI Miscellaneous Registers722.10.1 QPI_0_PLL_STATUS QPI_1_PLL_STATUS722.10.2 QPI_0_PLL_RATIO QPI_1_PLL_RATIO722.11 Integrated Memory Controller Control Registers732.11.1 MC_CONTROL732.11.2 MC_STATUS742.11.3 MC_SMI_DIMM_ERROR_STATUS742.11.4 MC_SMI_CNTRL752.11.5 MC_RESET_CONTROL762.11.6 MC_CHANNEL_MAPPER762.11.7 MC_MAX_DOD772.11.8 MC_RD_CRDT_INIT772.11.9 MC_CRDT_WR_THLD782.11.10 MC_SCRUBADDR_LO792.11.11 MC_SCRUBADDR_HI792.12 TAD - Target Address Decoder Registers802.12.1 TAD_DRAM_RULE_0 TAD_DRAM_RULE_1 TAD_DRAM_RULE_2 TAD_DRAM_RULE_3 TAD_DRAM_RULE_4 TAD_DRAM_RULE_5 TAD_DRAM_RULE_6 TAD_DRAM_RULE_7802.12.2 TAD_INTERLEAVE_LIST_0 TAD_INTERLEAVE_LIST_1 TAD_INTERLEAVE_LIST_2 TAD_INTERLEAVE_LIST_3 TAD_INTERLEAVE_LIST_4 TAD_INTERLEAVE_LIST_5 TAD_INTERLEAVE_LIST_6 TAD_INTERLEAVE_LIST_7812.13 Integrated Memory Controller RAS Registers822.13.1 MC_SSRCONTROL822.13.2 MC_SCRUB_CONTROL832.13.3 MC_RAS_ENABLES832.13.4 MC_RAS_STATUS832.13.5 MC_SSRSTATUS842.13.6 MC_COR_ECC_CNT_0 MC_COR_ECC_CNT_1 MC_COR_ECC_CNT_2 MC_COR_ECC_CNT_3 MC_COR_ECC_CNT_4 MC_COR_ECC_CNT_5842.14 Integrated Memory Controller Test Registers852.14.1 MC_TEST_ERR_RCV1852.14.2 MC_TEST_ERR_RCV0852.14.3 MC_TEST_PH_CTR862.14.4 MC_TEST_PH_PIS862.14.5 MC_TEST_PAT_GCTR862.14.6 MC_TEST_PAT_BA872.14.7 MC_TEST_PAT_IS872.14.8 MC_TEST_PAT_DCD872.15 Integrated Memory Controller Channel Control Registers882.15.1 MC_CHANNEL_0_DIMM_RESET_CMD MC_CHANNEL_1_DIMM_RESET_CMD MC_CHANNEL_2_DIMM_RESET_CMD882.15.2 MC_CHANNEL_0_DIMM_INIT_CMD MC_CHANNEL_1_DIMM_INIT_CMD MC_CHANNEL_2_DIMM_INIT_CMD882.15.3 MC_CHANNEL_0_DIMM_INIT_PARAMS MC_CHANNEL_1_DIMM_INIT_PARAMS MC_CHANNEL_2_DIMM_INIT_PARAMS892.15.4 MC_CHANNEL_0_DIMM_INIT_STATUS MC_CHANNEL_1_DIMM_INIT_STATUS MC_CHANNEL_2_DIMM_INIT_STATUS912.15.5 MC_CHANNEL_0_DDR3CMD MC_CHANNEL_1_DDR3CMD MC_CHANNEL_2_DDR3CMD922.15.6 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT932.15.7 MC_CHANNEL_0_MRS_VALUE_0_1 MC_CHANNEL_1_MRS_VALUE_0_1 MC_CHANNEL_2_MRS_VALUE_0_1932.15.8 MC_CHANNEL_0_MRS_VALUE_2 MC_CHANNEL_1_MRS_VALUE_2 MC_CHANNEL_2_MRS_VALUE_2942.15.9 MC_CHANNEL_0_RANK_PRESENT MC_CHANNEL_1_RANK_PRESENT MC_CHANNEL_2_RANK_PRESENT942.15.10 MC_CHANNEL_0_RANK_TIMING_A MC_CHANNEL_1_RANK_TIMING_A MC_CHANNEL_2_RANK_TIMING_A952.15.11 MC_CHANNEL_0_RANK_TIMING_B MC_CHANNEL_1_RANK_TIMING_B MC_CHANNEL_2_RANK_TIMING_B982.15.12 MC_CHANNEL_0_BANK_TIMING MC_CHANNEL_1_BANK_TIMING MC_CHANNEL_2_BANK_TIMING992.15.13 MC_CHANNEL_0_REFRESH_TIMING MC_CHANNEL_1_REFRESH_TIMING MC_CHANNEL_2_REFRESH_TIMING992.15.14 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING MC_CHANNEL_2_CKE_TIMING1002.15.15 MC_CHANNEL_0_ZQ_TIMING MC_CHANNEL_1_ZQ_TIMING MC_CHANNEL_2_ZQ_TIMING1002.15.16 MC_CHANNEL_0_RCOMP_PARAMS MC_CHANNEL_1_RCOMP_PARAMS MC_CHANNEL_2_RCOMP_PARAMS1012.15.17 MC_CHANNEL_0_ODT_PARAMS1 MC_CHANNEL_1_ODT_PARAMS1 MC_CHANNEL_2_ODT_PARAMS11012.15.18 MC_CHANNEL_0_ODT_PARAMS2 MC_CHANNEL_1_ODT_PARAMS2 MC_CHANNEL_2_ODT_PARAMS21022.15.19 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_RD1022.15.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_RD1032.15.21 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_WR1032.15.22 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_WR1032.15.23 MC_CHANNEL_0_WAQ_PARAMS MC_CHANNEL_1_WAQ_PARAMS MC_CHANNEL_2_WAQ_PARAMS1042.15.24 MC_CHANNEL_0_SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULER_PARAMS MC_CHANNEL_2_SCHEDULER_PARAMS1042.15.25 MC_CHANNEL_0_MAINTENANCE_OPS MC_CHANNEL_1_MAINTENANCE_OPS MC_CHANNEL_2_MAINTENANCE_OPS1052.15.26 MC_CHANNEL_0_TX_BG_SETTINGS MC_CHANNEL_1_TX_BG_SETTINGS MC_CHANNEL_2_TX_BG_SETTINGS1052.15.27 MC_CHANNEL_0_RX_BGF_SETTINGS MC_CHANNEL_1_RX_BGF_SETTINGS MC_CHANNEL_2_RX_BGF_SETTINGS1062.15.28 MC_CHANNEL_0_EW_BGF_SETTINGS MC_CHANNEL_1_EW_BGF_SETTINGS MC_CHANNEL_2_EW_BGF_SETTINGS1062.15.29 MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_2_EW_BGF_OFFSET_SETTINGS1062.15.30 MC_CHANNEL_0_ROUND_TRIP_LATENCY MC_CHANNEL_1_ROUND_TRIP_LATENCY MC_CHANNEL_2_ROUND_TRIP_LATENCY1072.15.31 MC_CHANNEL_0_PAGETABLE_PARAMS1 MC_CHANNEL_1_PAGETABLE_PARAMS1 MC_CHANNEL_2_PAGETABLE_PARAMS11072.15.32 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH21072.15.33 MC_TX_BG_CMD_OFFSET_SETTINGS_CH0 MC_TX_BG_CMD_OFFSET_SETTINGS_CH1 MC_TX_BG_CMD_OFFSET_SETTINGS_CH21082.15.34 MC_TX_BG_DATA_OFFSET_SETTINGS_CH0 MC_TX_BG_DATA_OFFSET_SETTINGS_CH1 MC_TX_BG_DATA_OFFSET_SETTINGS_CH21082.16 Integrated Memory Controller Channel Address Registers1092.16.1 MC_DOD_CH0_0 MC_DOD_CH0_1 MC_DOD_CH0_21092.16.2 MC_DOD_CH1_0 MC_DOD_CH1_1 MC_DOD_CH1_21102.16.3 MC_DOD_CH2_0 MC_DOD_CH2_1 MC_DOD_CH2_21112.16.4 MC_SAG_CH0_0 MC_SAG_CH0_1 MC_SAG_CH0_2 MC_SAG_CH0_3 MC_SAG_CH0_4 MC_SAG_CH0_5 MC_SAG_CH0_6 MC_SAG_CH0_7 MC_SAG_CH1_0 MC_S...1122.17 Integrated Memory Controller Channel Rank Registers1132.17.1 MC_RIR_LIMIT_CH0_0 MC_RIR_LIMIT_CH0_1 MC_RIR_LIMIT_CH0_2 MC_RIR_LIMIT_CH0_3 MC_RIR_LIMIT_CH0_4 MC_RIR_LIMIT_CH0_5 MC_RIR_...1132.17.2 MC_RIR_WAY_CH0_0 MC_RIR_WAY_CH0_1 MC_RIR_WAY_CH0_2 MC_RIR_WAY_CH0_3 MC_RIR_WAY_CH0_4 MC_RIR_WAY_CH0_5 MC_RIR_WAY_CH0_6 MC...1142.17.3 MC_RIR_WAY_CH1_0 MC_RIR_WAY_CH1_1 MC_RIR_WAY_CH1_2 MC_RIR_WAY_CH1_3 MC_RIR_WAY_CH1_4 MC_RIR_WAY_CH1_5 MC_RIR_WAY_CH1_6 MC...1152.17.4 MC_RIR_WAY_CH2_0 MC_RIR_WAY_CH2_1 MC_RIR_WAY_CH2_2 MC_RIR_WAY_CH2_3 MC_RIR_WAY_CH2_4 MC_RIR_WAY_CH2_5 MC_RIR_WAY_CH2_6 MC...1172.18 Memory Thermal Control1182.18.1 MC_THERMAL_CONTROL0 MC_THERMAL_CONTROL1 MC_THERMAL_CONTROL21182.18.2 MC_THERMAL_STATUS0 MC_THERMAL_STATUS1 MC_THERMAL_STATUS21192.18.3 MC_THERMAL_DEFEATURE0 MC_THERMAL_DEFEATURE1 MC_THERMAL_DEFEATURE21192.18.4 MC_THERMAL_PARAMS_A0 MC_THERMAL_PARAMS_A1 MC_THERMAL_PARAMS_A21192.18.5 MC_THERMAL_PARAMS_B0 MC_THERMAL_PARAMS_B1 MC_THERMAL_PARAMS_B21202.18.6 MC_COOLING_COEF0 MC_COOLING_COEF1 MC_COOLING_COEF21202.18.7 MC_CLOSED_LOOP0 MC_CLOSED_LOOP1 MC_CLOSED_LOOP21212.18.8 MC_THROTTLE_OFFSET0 MC_THROTTLE_OFFSET1 MC_THROTTLE_OFFSET21212.18.9 MC_RANK_VIRTUAL_TEMP0 MC_RANK_VIRTUAL_TEMP1 MC_RANK_VIRTUAL_TEMP21222.18.10 MC_DDR_THERM_COMMAND0 MC_DDR_THERM_COMMAND1 MC_DDR_THERM_COMMAND21222.18.11 MC_DDR_THERM_STATUS0 MC_DDR_THERM_STATUS1 MC_DDR_THERM_STATUS21232.19 Integrated Memory Controller Miscellaneous Registers1232.19.1 MC_DIMM_CLK_RATIO_STATUS1232.19.2 MC_DIMM_CLK_RATIO1243 DIMM Population Requirements1253.1 General Population Requirements1253.2 Populating DIMMs Within a Channel1263.2.1 DIMM Population for Three Slots per Channel1263.2.2 DIMM Population for Two Slots per Channel128Size: 1.88 MBPages: 130Language: EnglishOpen manual
