User ManualTable of ContentsFeatures1Configurations1Functional Description1Selection Guide1Logic Block Diagram (CY7C1246V18)2Logic Block Diagram (CY7C1257V18)2Logic Block Diagram (CY7C1248V18)3Logic Block Diagram (CY7C1250V18)3Pin Configurations4Pin Definitions6Functional Overview8Read Operations8Write Operations8Byte Write Operations8Double Data Rate Operation8Depth Expansion8Programmable Impedance8Echo Clocks8Valid Data Indicator (QVLD)9Delay Lock Loop (DLL)9Application Example9Truth Table9Write Cycle Descriptions10Write Cycle Descriptions10Write Cycle Descriptions11IEEE 1149.1 Serial Boundary Scan (JTAG)12Disabling the JTAG Feature12Test Access Port - Test Clock12Test Mode Select12Test Data-In (TDI)12Test Data-Out (TDO)12Performing a TAP Reset12TAP Registers12Instruction Register12Bypass Register12Boundary Scan Register12Identification (ID) Register12TAP Instruction Set12IDCODE13SAMPLE Z13SAMPLE/PRELOAD13BYPASS13EXTEST13EXTEST Output Bus Tri-State13Reserved13TAP Controller State Diagram14TAP Controller Block Diagram15TAP Electrical Characteristics15TAP AC Switching Characteristics16TAP Timing and Test Conditions16Identification Register Definitions17Scan Register Sizes17Instruction Codes17Boundary Scan Order18Power Up Sequence in DDR-II+ SRAM19Power Up Sequence19DLL Constraints19Power Up Waveforms19Maximum Ratings20Operating Range20Electrical Characteristics20DC Electrical Characteristics20AC Input Requirements20Capacitance21Thermal Resistance21AC Test Loads and Waveforms21Switching Characteristics22Switching Waveforms23Read/Write/Deselect Sequence[28, 29, 30]23Ordering Information24Package Diagram26Document History Page27Size: 643 KBPages: 27Language: EnglishOpen manual