User ManualTable of Contents1. About this Document61.1 Change Control61.1.1 Current Status61.1.2 Change History61.2 Conventions61.3 Scope61.4 References61.5 Terms and Abbreviations72. Functional Description82.1 Functional Overview82.2 Block Diagram92.3 Operating Modes102.3.1 Software Initialisation102.3.2 CAN Message Transfer102.3.3 Disabled Automatic Retransmission112.3.4 Test Mode112.3.4.1 Test Register (addresses 0x0B & 0x0A)112.3.4.2 Disable Watchdog Mode122.3.4.3 Silent Mode122.3.4.4 Loop Back Mode132.3.4.5 Loop Back combined with Silent Mode132.3.4.6 Software control of Pin CAN_TX142.3.4.7 No Message RAM Mode143. Programmer’s Model153.1 Hardware Reset Description163.2 CAN Protocol Related Registers173.2.1 CAN Control Register (addresses 0x01 & 0x00)173.2.2 Status Register (addresses 0x03 & 0x02)183.2.2.1 Status Interrupts193.2.3 Error Counter (addresses 0x05 & 0x04)193.2.4 Bit Timing Register (addresses 0x07 & 0x06)193.2.5 BRP Extension Register (addresses 0x0D & 0x0C)203.3 Message Interface Register Sets203.3.1 IFx Command Mask Registers213.3.1.1 Direction = Write213.3.1.2 Direction = Read223.3.2 IFx Command Request Registers223.3.3 IFx Message Buffer Registers233.3.3.1 IFx Mask Registers233.3.3.2 IFx Arbitration Registers233.3.3.3 IFx Message Control Registers243.3.3.4 IFx Data A and Data B Registers243.3.4 Message Object in the Message Memory243.4 Message Handler Registers273.4.1 Interrupt Register (addresses 0x09 & 0x08)273.4.2 Transmission Request Registers283.4.3 New Data Registers283.4.4 Interrupt Pending Registers283.4.5 Message Valid 1 Register293.5 Registers for Time Triggered Communication293.5.1 Trigger Memory Access Register (addresses 0x0F & 0x0E)293.5.2 IF1 Data B1 and B2 Registers for Trigger Memory Access293.5.3 TT Operation Mode Register (addresses 0x29 & 0x28)303.5.4 TT Matrix Limits1 Register (addresses 0x2B & 0x2A)313.5.5 TT Matrix Limits2 Register (addresses 0x2D & 0x2C)313.5.6 TT Application Watchdog Limit Register (addresses 0x2F & 0x2E)323.5.7 TT Interrupt Enable Register (addresses 0x31 & 0x30)323.5.8 TT Interrupt Vector Register (addresses 0x33 & 0x32)323.5.9 TT Global Time Register (addresses 0x35 & 0x34)343.5.10 TT Cycle Time Register (addresses 0x37 & 0x36)343.5.11 TT Local Time Register (addresses 0x39 & 0x38)343.5.12 TT Master State Register (addresses 0x3B & 0x3A)343.5.13 TT Cycle Count Register (addresses 0x3D & 0x3C)353.5.14 TT Error Level Register (addresses 0x3F & 0x3E)353.5.15 TUR Numerator Configuration Low Register (addresses 0x57 & 0x56)353.5.16 TUR Denominator Configuration Register (addresses 0x59 & 0x58)363.5.17 TUR Numerator Actual Registers (addresses 0x5B & 0x5A)363.5.18 TT Stop_Watch Register (addresses 0x61 & 0x60)363.5.19 TT Global Time Preset Register (addresses 0x65 & 0x64)373.5.20 TT Clock Control Register (addresses 0x67 & 0x66)373.5.21 TT Sync_Mark Register (addresses 0x69 & 0x68)383.5.22 TT Time Mark Register (addresses 0x6D & 0x6C)393.5.23 TT Gap Control Register (addresses 0x6F & 0x6E)394. CAN Application414.1 Internal CAN Message Handling414.1.1 Data Transfer Between IFx Registers and Message RAM414.1.2 Transmission of Messages in Event Driven CAN Communication424.1.3 Acceptance Filtering of Received Messages434.1.3.1 Reception of Data Frame434.1.3.2 Reception of Remote Frame434.1.4 Storing Received Messages in FIFO Buffers434.1.5 Receive / Transmit Priority444.2 Configuration of the Module444.2.1 Configuration of the Bit Timing454.2.1.1 Bit Time and Bit Rate454.2.1.2 Propagation Time Segment464.2.1.3 Phase Buffer Segments and Synchronisation474.2.1.4 Oscillator Tolerance Range504.2.1.5 Configuration of the CAN Protocol Controller504.2.1.6 Calculation of the Bit Timing Parameters514.2.1.7 Example for Bit Timing at high Baudrate524.2.1.8 Example for Bit Timing at low Baudrate534.2.2 Configuration of the Message Memory534.2.2.1 Configuration of a Transmit Object for Data Frames544.2.2.2 Configuration of a Single Receive Object for Data Frames544.2.2.3 Configuration of a FIFO Buffer554.2.2.4 Configuration of a Single Receive Object for Remote Frames554.3 CAN Communication564.3.1 Handling of Interrupts564.3.2 Updating a Transmit Object574.3.3 Changing a Transmit Object584.3.4 Reading Received Messages584.3.5 Requesting New Data for a Receive Object584.3.6 Reading from a FIFO Buffer585. TTCAN Application605.1 TTCAN Configuration605.1.1 TTCAN Timing605.1.2 Message Scheduling615.1.3 Trigger Memory625.1.4 Message Objects645.1.4.1 Reference Message645.1.4.2 Periodic Transmit Message645.1.4.3 Event Driven Transmit Message655.2 TTCAN Schedule Initialisation655.2.1 Time Slaves655.2.2 Potential Time Masters655.3 TTCAN Message Handling665.3.1 Message Reception665.3.2 Message Transmission665.3.2.1 Periodic Messages665.3.2.2 Event Driven Messages665.4 TTCAN Gap Control675.5 Stopwatch675.6 Local Time, Cycle Time, and Global Time and External Clock Synchronisation675.7 TTCAN Interrupt and Error Handling695.8 Configuration Example706. CPU Interface756.1 Customer Interface756.2 Timing of the WAIT output signal766.3 Interrupt Timing767. Appendix777.1 List of Figures77Size: 768 KBPages: 77Language: EnglishOpen manual