User ManualTable of ContentsCONTENTS4LIST OF FIGURES10LIST OF TABLES12INTRODUCTION14TERMS, ACRONYMS AND ABBREVIATIONS14DOCUMENTS15USER APPLICATIONS16STAND-ALONE ROUTER16NODE INTERFACE17EMBEDDED ROUTER17EXPANDING THE NUMBER OF ROUTER PORTS18FUNCTIONAL OVERVIEW21SPACEWIRE PORTS22EXTERNAL PORTS22CONFIGURATION PORT23ROUTING TABLE23ROUTING CONTROL LOGIC AND CROSSBAR23TIME-CODE PROCESSING24CONTROL/STATUS REGISTERS24PIN LOCATIONS25DEVICE INTERFACE31GLOBAL SIGNALS315.2 SPACEWIRE SIGNALS325.2.1 SpW-10X SpaceWire Signals325.2.2 SpaceWire Input Fail Safe Resistors355.2.3 Operation with 5V Powered LVDS Devices37EXTERNAL PORT DATA SIGNALS37TIME-CODE SIGNALS39STATUS INTERFACE SIGNALS41RESET CONFIGURATION SIGNALS425.7 POWER, GROUND, PLL AND LVDS SIGNALS455.7.1 General455.7.2 Decoupling455.7.3 LVDS Reference455.7.4 PLL External Components45INTERFACE OPERATIONS47EXTERNAL PORT INTERFACE OPERATION47TIME-CODE INTERFACE OPERATION48STATUS INTERFACE OPERATION49RESET CONFIGURATION INTERFACE OPERATION51SPACEWIRE ROUTER PACKET TYPES52PACKET ADDRESSES52PACKET PRIORITY53PACKET HEADER DELETION53INVALID ADDRESSES54DATA PACKETS557.6 COMMAND PACKETS557.6.1 Supported Commands557.6.2 Read Command567.6.3 Read Incrementing Command607.6.4 Read Modify Write Command657.6.5 Write Command707.6.6 Command Error Response747.6.7 Command Packet Cyclic Redundancy Check767.6.8 Local Source Path Address767.6.9 Source Path Address Field777.6.10 Command Packet Fill Bytes78CONTROL LOGIC AND OPERATIONAL MODES798.1 SPACEWIRE LINK CONTROL798.1.1 Default operating mode79Auto-Start79Link-Start79Link-Disable80Automatic deactivate driver mode80Setting the SpaceWire port transmit data rate828.2 GLOBAL SPACEWIRE LINK CONTROL848.2.1 Start on request mode858.2.2 Disable on Silence mode858.3 CONTROL LOGIC AND ROUTING868.3.1 Packet address error868.3.2 Arbitration868.3.2.1 Arbitration of packets with matching priority (1)878.3.2.2 Arbitration of packets with matching priority (2)888.3.2.3 Arbitration of packets with different priority (1)898.3.2.4 Arbitration of packets with different priority (2)908.3.3 Group Adaptive Routing928.3.3.1 Normal Group adaptive routing928.3.3.2 Group adaptive routing when busy928.3.3.3 Group adaptive routing when ports not ready938.3.4 Loop-back with Self-Addressing938.3.5 Packet Blocking958.3.5.1 Blocked destination958.3.5.2 Stalled source988.3.5.3 Waiting for an output port101REGISTER DEFINITIONS103INTERNAL MEMORY MAP103REGISTER ADDRESSES SUMMARY104GROUP ADAPTIVE ROUTING TABLE REGISTERS1059.4 PORT CONTROL/STATUS REGISTERS1089.4.1 Generic port control/status register fields.1089.4.2 Configuration port control/status register fields.1099.4.3 SpaceWire port control/status register bits.1129.4.4 External port control/status register bits1159.5 ROUTER CONTROL/STATUS REGISTERS1159.5.1 Network Discovery Register1159.5.2 Router Identity Register1169.5.3 Router Control Register1179.5.4 Error active Register120Time-Code Register121Device Manufacturer and Chip ID Register122General Purpose Register123Time-Code Enable Register123Transmit Clock Control Register124Destination Key Register127Unused Registers and Register Bits127Empty packets127WRITING TO A READ-ONLY REGISTER127SWITCHING CHARACTERISTICS128CLOCK AND RESET TIMING PARAMETERS128SERIAL SIGNALS TIMING PARAMETERS128EXTERNAL PORT TIMING PARAMETERS129TIME-CODE INTERFACE TIMING PARAMETERS130ERROR/STATUS INTERFACE TIMING PARAMETERS13110.6 LATENCY AND JITTER13310.6.1 Clock Periods13310.6.2 Switching Latency13310.6.3 Router Latency13310.6.4 Time-code Latency13410.6.5 Time-code Jitter13510.6.6 200M bits/s Input and Output Bit Rate Example135ELECTRICAL CHARACTERISTICS136DC CHARACTERISTICS136ABSOLUTE MAXIMUM RATINGS137RELIABILITY INFORMATION137APPLICATION GUIDELINES138EXAMPLE CIRCUIT DIAGRAM13812.2 PCB DESIGN AND LAYOUT GUIDELINES14012.2.1 CLK14012.2.2 RST_N14012.2.3 Chip Test Signals14012.2.4 Power and Decoupling14012.2.5 Ground14012.2.6 SpaceWire14012.2.7 External Ports14112.2.8 Time-code Interface14112.2.9 Status / Power On Configuration Interface14112.2.10 PLL142ANOMALIES AND WARNINGS143ANOMALIES143WARNINGS14313.3 RESET ANOMALY14513.3.1 Data Strobe Reset Waveform14513.3.2 Data Strobe Disable Waveform14713.3.3 Reset Anomaly Workarounds14713.4 PARITY ERROR ANOMALY14813.4.1 Parity Error Action14813.4.2 Parity Error Anomaly14813.4.3 Parity Error Workaround149TECHNICAL SUPPORT150DOCUMENT CHANGES151ISSUE 3.3 TO ISSUE 3.4151ISSUE 3.2 TO ISSUE 3.3151ISSUE 3.1 TO ISSUE 3.2151ISSUE 3.0 TO ISSUE 3.1152ISSUE 2.5 TO ISSUE 3.0152ISSUE 2.4 TO ISSUE 2.5153ISSUE 2.3 TO ISSUE 2.4153ISSUE 2.2 TO ISSUE 2.3153ISSUE 2.1 TO ISSUE 2.2154ISSUE 2.0 TO ISSUE 2.1154ISSUE 1.7 TO ISSUE 2.0154ISSUE 1.6 TO ISSUE 1.7154ISSUE 1.5 TO ISSUE 1.6154ISSUE 1.4 TO ISSUE 1.5154ISSUE 1.3 TO ISSUE 1.4154ISSUE 1.2 TO ISSUE 1.3154ISSUE 1.1 TO ISSUE 1.2155ISSUE 1.0 TO ISSUE 1.1155FIGURE 2-1 STAND-ALONE ROUTER16FIGURE 2-2 NODE INTERFACE17FIGURE 2-3 EMBEDDED ROUTER18FIGURE 2-4 EXPANDING THE NUMBER OF SPACEWIRE PORTS (1)19FIGURE 2-5 EXPANDING THE NUMBER OF SPACEWIRE PORTS (2)20FIGURE 3-1 SPACEWIRE ROUTER BLOCK DIAGRAM22FIGURE 5-1 LVDS RECEIVER FAIL-SAFE RESISTORS35FIGURE 5-2 CONFIGURATION INTERFACE TIMING SPECIFICATION42FIGURE 5-3 PLL WITH EXTERNAL COMPONENTS46FIGURE 6-1 EXTERNAL PORT WRITE TIMING SPECIFICATION47FIGURE 6-2 EXTERNAL PORT READ TIMING SPECIFICATION48FIGURE 6-3 TIME-CODE INPUT INTERFACE48FIGURE 6-4 TIME-CODE OUTPUT INTERFACE49FIGURE 6-5 TIME-CODE RESET INTERFACE49FIGURE 6-6 STATUS MULTIPLEXER OUTPUT INTERFACE49FIGURE 6-7 RESET CONFIGURATION INTERFACE TIMING SPECIFICATION51FIGURE 7-1 NORMAL ROUTER DATA PACKETS55FIGURE 7-2 COMMAND PACKET FORMAT55FIGURE 7-3 READ SINGLE ADDRESS COMMAND FORMAT57FIGURE 7-4 READ SINGLE ADDRESS REPLY PACKET FORMAT59FIGURE 7-5 READ INCREMENTING ADDRESS COMMAND FORMAT62FIGURE 7-6 READ INCREMENTING ADDRESS REPLY PACKET FORMAT64FIGURE 7-7 READ-MODIFY-WRITE COMMAND PACKET FORMAT66FIGURE 7-8 READ-MODIFY-WRITE EXAMPLE OPERATION68FIGURE 7-9 READ-MODIFY-WRITE REPLY PACKET FORMAT69FIGURE 7-10 WRITE SINGLE ADDRESS COMMAND PACKET71FIGURE 7-11 WRITE SINGLE ADDRESS REPLY PACKET73FIGURE 7-12 SOURCE PATH ADDRESS FIELD DECODING78FIGURE 7-13 SOURCE PATH ADDRESSES IN REPLY PACKET78FIGURE 7-14 NORMAL CONFIGURATION PACKET HEADER STRUCTURE78FIGURE 7-15 FILL BYTES CONFIGURATION HEADER STRUCTURE78FIGURE 8-1 DEACTIVATE DRIVER OPERATING MODE81FIGURE 8-2 DEACTIVATED LDVS DRIVER OUTPUT81FIGURE 8-4 START ON REQUEST MODE85FIGURE 8-5 DISABLE ON SILENCE MODE86FIGURE 8-6 ARBITRATION OF TWO PACKETS WITH MATCHING PRIORITY.87FIGURE 8-7 ARBITRATION OF THREE PACKETS WITH MATCHING PRIORITY88FIGURE 8-8 ARBITRATION OF TWO PACKETS WITH DIFFERENT PRIORITY (1)89FIGURE 8-9 ARBITRATION OF TWO PACKETS WITH DIFFERENT PRIORITY (2)91FIGURE 8-10 NORMAL GROUP ADAPTIVE ROUTING92FIGURE 8-11 GROUP ADAPTIVE ROUTING WHEN OTHER PORTS BUSY93FIGURE 8-12 GROUP ADAPTIVE ROUTING WHEN PORTS NOT READY93FIGURE 8-13 PACKET SELF-ADDRESSING MODE94FIGURE 8-14 DESTINATION NODE BLOCKED (A)96FIGURE 8-15 DESTINATION NODE BLOCKED (B)96FIGURE 8-16 DESTINATION NODE BLOCKED (C)97FIGURE 8-17 DESTINATION NODE BLOCKED: WATCHDOG MODE (A)97FIGURE 8-18 DESTINATION NODE BLOCKED: WATCHDOG MODE (B)97FIGURE 8-19 DESTINATION NODE BLOCKED: WATCHDOG MODE (C)98FIGURE 8-20 DESTINATION NODE BLOCKED: WATCHDOG MODE (D)98FIGURE 8-21 SOURCE NODE STALLED (A)99FIGURE 8-22 SOURCE NODE STALLED (B)99FIGURE 8-23 SOURCE NODE STALLED (C)99FIGURE 8-24 SOURCE NODE STALLED (D)99FIGURE 8-25 SOURCE NODE STALLED: WATCHDOG MODE (A)100FIGURE 8-26 SOURCE NODE STALLED: WATCHDOG MODE (B)100FIGURE 8-27 SOURCE NODE STALLED: WATCHDOG MODE (C)100FIGURE 8-28 SOURCE NODE STALLED: WATCHDOG MODE (D)100FIGURE 9-1 ROUTER INTERNAL MEMORY MAP103FIGURE 9-2 GAR REGISTER FIELDS105FIGURE 9-3 SPACEWIRE PORT CONTROL/STATUS REGISTER FIELDS112FIGURE 9-4 NETWORK DISCOVERY REGISTER FIELDS116FIGURE 9-5 ROUTER CONTROL REGISTER FIELDS117FIGURE 9-6 ERROR ACTIVE REGISTER FIELDS120FIGURE 9-7 TIME-CODE REGISTER FIELDS121FIGURE 9-8 DEVICE MANUFACTURER AND CHIP ID REGISTER FIELDS122FIGURE 9-9 TIME-CODE ENABLE REGISTER FIELDS123FIGURE 9-10 TRANSMIT CLOCK CONTROL REGISTER125FIGURE 10-1 DS MINIMUM CONSECUTIVE EDGE SEPARATION128FIGURE 10-2 EXTERNAL PORT INPUT FIFO TIMING PARAMETERS129FIGURE 10-3 EXTERNAL PORT OUTPUT FIFO TIMING PARAMETERS129FIGURE 10-4 TIME-CODE INPUT INTERFACE130FIGURE 10-5 TIME-CODE OUTPUT INTERFACE131FIGURE 10-6 TIME-CODE TIME_CTR_RST INTERFACE131FIGURE 12-1 PLL LAYOUT RECOMMENDATIONS142FIGURE 13-1 RESET WAVEFORM146FIGURE 13-2 RESET WAVEFORM WITH DATA AND STROBE BOTH HIGH146FIGURE 13-3 GLITCHES ON DATA OR STROBE DURING RESET146FIGURE 13-4 SIMULTANEOUS TRANSITION OF DATA AND STROBE DURING RESET146FIGURE 13-5 LINK DISCONNECT WAVEFORMS147FIGURE 13-6 DATA AFTER PARITY ERROR ANOMALY148FIGURE 13-7 NO ERROR END OF PACKET INSERTED AFTER PARITY ERROR149TABLE 1-1 APPLICABLE DOCUMENTS15TABLE 1-2 REFERENCE DOCUMENTS15TABLE 5-1 GLOBAL SIGNALS32TABLE 5-2 DATA AND STROBE SPACEWIRE SIGNALS33TABLE 5-3 EXTERNAL PORT INTERFACE SIGNALS37TABLE 5-4 TIME-CODE SIGNALS39TABLE 5-5 LINK ERROR INDICATION SIGNALS41TABLE 5-6 RESET CONFIGURATION SIGNALS43TABLE 5-7 POWER, GROUND AND SPECIAL SIGNALS45TABLE 6-1 MULTIPLEXED STATUS PINS BIT ASSIGNMENT50TABLE 7-1 PACKET ADDRESS MAPPING52TABLE 7-2 PACKET PRIORITY MAPPING53TABLE 7-3 PACKET HEADER DELETION MAPPING54TABLE 7-4 SUPPORTED RMAP COMMAND CODES56TABLE 7-5 READ SINGLE ADDRESS CHARACTERISTICS57TABLE 7-6 READ SINGLE ADDRESS COMMAND PACKET FIELDS58TABLE 7-7 READ SINGLE ADDRESS REPLY PACKET FIELDS59TABLE 7-8 READ INCREMENTING ADDRESS CHARACTERISTICS61TABLE 7-9 READ INCREMENTING ADDRESS COMMAND PACKET FIELDS62TABLE 7-10 READ INCREMENTING ADDRESS REPLY PACKET FIELDS64TABLE 7-11 READ-MODIFY-WRITE COMMAND CHARACTERISTICS65TABLE 7-12 READ-MODIFY-WRITE COMMAND PACKET FIELDS67TABLE 7-13 READ-MODIFY-WRITE REPLY PACKET FIELDS69TABLE 7-14 WRITE COMMAND CHARACTERISTICS70TABLE 7-15 WRITE SINGLE ADDRESS COMMAND PACKET FIELDS71TABLE 7-16 WRITE SINGLE ADDRESS REPLY PACKET FIELDS73TABLE 7-17 CONFIGURATION PORT ERRORS SUMMARY74TABLE 7-18 SOURCE PATH ADDRESS REFERENCE TABLE77TABLE 8-1 SETTING SPACEWIRE TRANSMIT DATA RATE83TABLE 9-1 TYPES OF REGISTER WITHIN CONFIGURATION PORT104TABLE 9-2 CONFIGURATION REGISTER ADDRESSES105TABLE 9-3 GAR TABLE REGISTER DESCRIPTION107TABLE 9-4 CONFIGURATION PORT CONTROL/STATUS REGISTER FIELDS108TABLE 9-5 CONFIGURATION PORT CONTROL/STATUS REGISTER FIELDS110TABLE 9-6 SPACEWIRE PORT CONTROL/STATUS REGISTER FIELDS.113TABLE 9-7 EXTERNAL PORT CONTROL/STATUS FIELDS115TABLE 9-8 NETWORK DISCOVERY REGISTER FIELDS116TABLE 9-9 ROUTER IDENTITY REGISTER FIELD117TABLE 9-10 ROUTER CONTROL REGISTER FIELDS118TABLE 9-11 ERROR ACTIVE REGISTER FIELDS121TABLE 9-12 TIME-CODE REGISTER FIELDS122TABLE 9-13 DEVICE MANUFACTURER AND CHIP ID REGISTER FIELDS122TABLE 9-14 TIME-CODE ENABLE REGISTER FIELDS124TABLE 9-15 TRANSMIT CLOCK CONTROL REGISTER BITS126TABLE 9-16 DESTINATION KEY REGISTER127TABLE 10-1 CLOCK AND RESET TIMING PARAMETERS128TABLE 10-2 SERIAL SIGNAL TIMING PARAMETERS129TABLE 10-3 EXTERNAL PORT TIMING PARAMETERS130TABLE 10-4 TIME-CODE INTERFACE TIMING PARAMETERS131TABLE 10-5 STATUS MULTIPLEXER TIMING PARAMETERS132TABLE 10-6 SPACEWIRE ROUTER LATENCY AND JITTER MEASUREMENTS (BIT RATE = 200MBITS/S135TABLE 11-1 OPERATING CONDITIONS136TABLE 11-2 ABSOLUTE MAXIMUM RATINGS137TABLE 11-3 RELIABILTY INFORMATION137Size: 1.03 MBPages: 155Language: EnglishOpen manual