User ManualTable of ContentsRealView Platform Baseboard for ARM926EJ-S User Guide1Contents5List of Tables9List of Figures13Preface17About this manual18Product revision status18Intended audience18Using this manual18Conventions19Further reading22Feedback25Feedback on this product25Feedback on this manual25Introduction271.1 About the PB926EJ-S281.2 PB926EJ-S architecture301.2.1 System architecture321.2.2 ARM926EJ-S PXP Development Chip331.2.3 PB926EJ-S FPGA331.2.4 Displays331.2.5 RealView Logic Tile expansion331.2.6 Memory341.2.7 Clock generators341.2.8 Debug and test interfaces341.3 Precautions351.3.1 Ensuring safety351.3.2 Preventing damage35Getting Started372.1 Setting up the RealView Platform382.2 Setting the configuration switches392.2.1 Boot memory configuration392.2.2 LED indicators412.2.3 Boot Monitor configuration432.3 Connecting JTAG debugging equipment442.4 Connecting the Trace Port Analyzer462.4.1 About using trace482.5 Supplying power492.6 Using the PB926EJ-S Boot Monitor and platform library502.6.1 Running the Boot Monitor502.6.2 Rebuilding the Boot Monitor542.6.3 Loading Boot Monitor into NOR flash562.6.4 Redirecting character output to hardware devices572.6.5 Rebuilding the platform library582.6.6 Building an application with the platform library592.6.7 Loading and running an application from NOR flash602.6.8 Using a boot script to run an image automatically61Hardware Description633.1 ARM926EJ-S PXP Development Chip653.1.1 ARM926EJ-S PXP Development Chip overview653.1.2 Configuration control693.1.3 AHB bridges and the bus matrix723.1.4 Memory interface773.1.5 AHB monitor783.2 FPGA793.2.1 FPGA configuration803.3 Reset controller843.3.1 Reset and reconfiguration logic843.3.2 Reset level863.3.3 Memory aliasing at reset893.3.4 Reset signals913.3.5 Reset timing943.4 Power supply control953.5 Clock architecture973.5.1 ARM926EJ-S PXP Development Chip clocks1013.5.2 RealView Logic Tile clocks1143.5.3 Peripheral clocks1163.5.4 Clock multiplexor logic1163.6 Advanced Audio Codec Interface, AACI1183.7 Character LCD controller1213.8 CLCDC interface1233.9 DMA1273.10 Ethernet interface1303.10.1 About the SMSC LAN91C1111313.11 GPIO interface1333.12 Interrupts1343.13 Keyboard/Mouse Interface, KMI1363.14 Memory Card Interface, MCI1373.14.1 MMC or SD operation1373.14.2 Card insertion and removal1383.14.3 Card interface description1383.15 PCI interface1413.16 Serial bus interface1423.17 Smart Card interface, SCI1433.18 Synchronous Serial Port, SSP1463.19 User switches and LEDs1493.20 UART interface1503.21 USB interface1543.22 Test, configuration, and debug interfaces1563.22.1 JTAG and USB debug port support1583.22.2 ChipScope integrated logic analyzer1663.22.3 Embedded trace support166Programmer’s Reference1674.1 Memory map1694.2 Configuration and initialization1754.2.1 Remapping of boot memory1754.2.2 Memory characteristics1814.3 Status and system control registers1834.3.1 ID Register, SYS_ID1874.3.2 Switch Register, SYS_SW1874.3.3 LED Register, SYS_LED1884.3.4 Oscillator registers, SYS_OSCx1894.3.5 Lock Register, SYS_LOCK1904.3.6 100Hz Counter, SYS_100HZ1914.3.7 Configuration registers SYS_CFGDATAx1914.3.8 Flag registers, SYS_FLAGx and SYS_NVFLAGx1964.3.9 Reset Control Register, SYS_RESETCTL1974.3.10 PCI Control Register, SYS_PCICTL1974.3.11 MCI Register, SYS_MCI1974.3.12 Flash Control Register, SYS_FLASH1984.3.13 CLCD Control Register, SYS_CLCD1984.3.14 2.2 inch LCD Control Register SYS_CLCDSER2004.3.15 Boot Select Register, SYS_BOOTCS2004.3.16 24MHz Counter, SYS_24MHZ2024.3.17 Miscellaneous System Control Register, SYS_MISC2024.3.18 DMA peripheral map registers, SYS_DMAPSRx2034.3.19 Oscillator reset registers, SYS_OSCRESETx2054.3.20 Oscillator test registers, SYS_TEST_OSCx2064.4 AHB monitor2074.5 Advanced Audio CODEC Interface, AACI2084.5.1 PrimeCell Modifications2084.6 Character LCD display2104.7 Color LCD Controller, CLCDC2134.7.1 PrimeCell Modifications2144.7.2 Display resolutions and display memory organization2144.8 Direct Memory Access Controller and mapping registers2184.9 Ethernet2214.10 General Purpose Input/Output, GPIO2224.11 Interrupt controllers2234.11.1 Primary interrupt controller2244.11.2 Secondary interrupt controller2274.11.3 Handling interrupts2294.12 Keyboard and Mouse Interface, KMI2334.13 MBX2344.14 MOVE video coprocessor2354.15 MultiMedia Card Interfaces, MCIx2364.16 MultiPort Memory Controller, MPMC2374.16.1 Register values2374.17 PCI controller2404.17.1 Control registers2414.17.2 PCI configuration2454.18 Real Time Clock, RTC2514.19 Serial bus interface2524.20 Smart Card Interface, SCI2544.21 Synchronous Serial Port, SSP2554.22 Synchronous Static Memory Controller, SSMC2574.22.1 Register values2584.23 System Controller2614.24 Timers2624.25 UART2634.25.1 PrimeCell Modifications2644.26 USB interface2654.27 Vector Floating Point, VFP92664.28 Watchdog267Signal Descriptions269A.1 Synchronous Serial Port interface270A.2 Smart Card interface271A.3 UART interface273A.4 USB interface274A.5 Audio CODEC interface275A.6 MMC and SD flash card interface276A.7 CLCD display interface278A.8 VGA display interface281A.9 GPIO interface282A.10 Keyboard and mouse interface283A.11 Ethernet interface284A.12 RealView Logic Tile header connectors285A.12.1 HDRX signals286A.12.2 HDRY signals290A.12.3 HDRZ294A.13 Test and debug connections301A.13.1 Overview of test points302A.13.2 JTAG304A.13.3 USB debug port304A.13.4 Trace connector pinout305A.13.5 Embedded logic analyzer306A.13.6 AHB monitor306A.13.7 FPGA debug connector pinout308Specifications309B.1 Electrical specification310B.1.1 Bus interface characteristics310B.1.2 Current requirements311B.2 Clock rate restrictions313B.2.1 AHB bus timing314B.2.2 Memory timing315B.2.3 Peripheral timing315B.3 Mechanical details317CLCD Display and Adaptor Board319C.1 About the CLCD display and adaptor board320C.2 Installing the CLCD display324C.2.1 Configuration325C.2.2 LCD power control325C.3 Touchscreen controller interface329C.3.1 Touchscreen interface architecture329C.3.2 Touchscreen controller programmer’s interface331C.4 Connectors333C.4.1 Interface connector333C.4.2 LCD prototyping connector334C.4.3 Touchscreen prototyping connector335C.4.4 Inverter prototyping connector335C.4.5 A/D and keypad connector336C.5 Mechanical layout337PCI Backplane and Enclosure339D.1 Connecting the PB926EJ-S to the PCI enclosure340D.1.1 Setting the backplane configuration switches342D.1.2 Connecting two PB926EJ-S boards343D.2 Backplane hardware344D.2.1 JTAG signals347D.3 Connectors348D.3.1 Power connector348D.3.2 Logic analyzer connector349D.3.3 JTAG connector350Memory Expansion Boards351E.1 About memory expansion352E.1.1 Operation without expansion memory353E.1.2 Memory board configuration353E.2 Fitting a memory board355E.3 EEPROM contents356E.4 Connector pinout363E.4.1 Expansion connector363E.5 Mechanical layout370RealView Logic Tile371F.1 About the RealView Logic Tile372F.2 Fitting a RealView Logic Tile373F.3 Header connectors374F.3.1 JTAG375F.3.2 Variable I/O levels375F.3.3 RealView Logic Tile I/O376F.3.4 RealView Logic Tile clocks377F.3.5 AHB buses used by the FPGA and RealView Logic Tiles381F.3.6 Reset384Configuring the USB Debug Connection385G.1 Installing the RealView ICE Micro Edition driver386G.1.1 Installing the RealView Developer Suite386G.1.2 Installing the RealView ICE Micro Edition driver on Windows 98SE386G.1.3 Installing the RealView ICE Micro Edition driver on Windows 2000387G.1.4 Installing the RealView ICE Micro Edition driver on Windows XP Professional388G.2 Changes to RealView Debugger389G.3 Using the USB debug port to connect RealView Debugger390G.3.1 Configuration390G.4 Using the Debug tab of the RealView Debugger Register pane394G.4.1 Global Properties395G.4.2 Device Properties396G.4.3 Semihosting Properties397Index399A399B399C399D400E400F400G400I400J400K400L400M400N401P401R401S401T402U402V402W402Size: 4.26 MBPages: 402Language: EnglishOpen manual
