Intel Video Game Controller Intel Gigabit Ethernet Controllers User Manual
294
Software Developer’s Manual
Register Descriptions
13.4.21
Interrupt Mask Clear Register
IMC (000D8h; W)
Software uses this register to disable an interrupt. Interrupts are presented to the bus interface only
when the mask bit is set to 1b and the cause bit set to 1b. The status of the mask bit is reflected in
the Interrupt Mask Set/Read Register (see
the Interrupt Mask Set/Read Register (see
), and the status of the cause bit is
reflected in the Interrupt Cause Read Register (see
Software blocks interrupts by clearing the corresponding mask bit. This is accomplished by writing
a 1b to the corresponding bit in this register. Bits written with 0b are unchanged (their mask status
does not change).
does not change).
RXSEQ
3
X
Sets mask for Receive Sequence Error.
This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.
This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.
RXDMT0
4
X
Sets mask for Receive Descriptor Minimum Threshold hit.
Reserved
5
X
Reserved
Should be written with 0b to ensure future compatibility.
Should be written with 0b to ensure future compatibility.
RXO
6
X
Sets mask for on Receiver FIFO Overrun.
RXT0
7
X
Sets mask for Receiver Timer Interrupt.
Reserved
8
X
Reserved
Should be written with 0b to ensure future compatibility.
Should be written with 0b to ensure future compatibility.
MDAC
9
X
Sets mask for MDI/O Access Complete Interrupt.
RXCFG
10
X
Sets mask for Receiving /C/ ordered sets.
This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.
This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.
Reserved
11
X
Reserved
Should be written with 0b to ensure future compatibility (not
applicable to the 82544GC/EI).
Should be written with 0b to ensure future compatibility (not
applicable to the 82544GC/EI).
PHYINT
12
X
Sets mask for PHY Interrupt (not applicable to the 82544GC/EI).
This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.
This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.
GPI
14:11
X
Sets mask for General Purpose Interrupts (82544GC/EI only).
GPI
14:13
X
Sets mask for General Purpose Interrupts.
TXD_LOW
15
X
Sets the mask for Transmit Descriptor Low Threshold hit (not
applicable to the 82544GC/EI).
applicable to the 82544GC/EI).
SRPD
16
X
Sets mask for Small Receive Packet Detection (not applicable to
the 82544GC/EI).
the 82544GC/EI).
Reserved
31:17
0b
Reserved
Should be written with 0b to ensure future compatibility.
Should be written with 0b to ensure future compatibility.
Field
Bit(s)
Initial
Value
Value
Description