Intel 41210 User Manual

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98
Intel
®
 41210 Serial to Parallel PCI Bridge Developer’s Manual
Register Description
12.2.39
Offset 6Dh: PM_NXTP—Power Management Next Item 
Pointer
12.2.40
Offset 6Eh: PM_PMC—Power Management Capabilities
Table 73. 
Offset 6Dh: PM_NXTP—Power Management Next Item Pointer
Bits
Type
Reset
Description
7:0
RO
D8h
Next Pointer:
 This field points to the PCI-X capability as the next capability.
Table 74. 
Offset 6Eh: PM_PMC—Power Management Capabilities
Bits
Type
Reset
Description
15:11
RO
19h
PME_Support:
 PME assertion is supported when in D3hot. PME assertion from D3cold is 
not supported.
10
RO
0b
D2 Support:
 Not supported
9
RO
0b
D1 Support:
 Not supported
8:6
RO
000b
Auxiliary Current:
 Auxiliary power is not supported.
5
RO
0b
DSI:
 Device-specific initialization is not required when transitioning to D0 from D3hot state. 
This bit is zero.
4
RsvdP
0b
Preserved
3
RO
0b
PME Clock:
 Does not apply to PCI Express*. Hard-wired to 0.
2:0
RO
2h
Version:
 PM implementation is compliant with PCI Bus Power Management Interface 
Specification
, Revision 1.1.