Intel 41210 User Manual
Intel
®
41210 Serial to Parallel PCI Bridge Developer’s Manual
67
Clock and Reset
10.2.4
Software PCI Reset (SBR—Secondary Bus Reset)
Commonly referred to as the Secondary Bus Reset (SBR), the software PCI reset is initiated by a
write to the bridge control register and resets only the particular PCI segment. This reset can be
used for various reasons, including but not limited to the following:
write to the bridge control register and resets only the particular PCI segment. This reset can be
used for various reasons, including but not limited to the following:
•
Recovering from error conditions on the secondary bus
•
Redoing enumeration
•
Changing the operating frequency of the bus (33/66/100/133 MHz)
•
Changing the operating mode of the bus (PCI or PCI-X)
This reset is synchronous to the PCI clock domain in which it is used. SBR is strictly restricted to
the particular PCI segment and affects neither the other PCI segment nor the rest of the 41210
Bridge logic. Writes to the bridge configuration register with a new frequency or bus mode have no
effect until the SBR is completed (see
the particular PCI segment and affects neither the other PCI segment nor the rest of the 41210
Bridge logic. Writes to the bridge configuration register with a new frequency or bus mode have no
effect until the SBR is completed (see
).
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