Nokia 6020b Service Manual
Issue 1 03/2005
COMPANY CONFIDENTIAL
53
Copyright © 2005 Nokia. All Rights Reserved.
RM-31
7 - System Module
7 - System Module
Nokia Customer Care
In GMSK mode, the output signal of the RF ASIC has constant level as the ALC amplifiers are
set to constant gain. The different power levels are generated by the gain variation of the power
amplifier.
set to constant gain. The different power levels are generated by the gain variation of the power
amplifier.
In EDGE mode, the ALC amplifiers generate the different power levels and the PA is set to con-
stant gain.
stant gain.
Frequency synthesizer signals
The reference oscillator is implemented as Voltage Controlled Temperature Compensated
Crystal Oscillator (VCTCXO) module. The component is located in the Small Signal chamber.
The VCTCXO generates the clock frequency of 26 MHz.
Crystal Oscillator (VCTCXO) module. The component is located in the Small Signal chamber.
The VCTCXO generates the clock frequency of 26 MHz.
The reference oscillator has two functions:
• Reference frequency for the PLL synthesizer.
• System clock for baseband part. The frequency is buffered in the RF ASIC and
fed to the UPP (signal VCTCXO = 26 MHz, output REFOUT of the RF ASIC).
fed to the UPP (signal VCTCXO = 26 MHz, output REFOUT of the RF ASIC).
The frequency of the VCTCXO is locked into the frequency of the base station with the help of
the AFC signal. This AFC voltage is generated in the UEM by an 11 bit D/A converter and tunes
the oscillator.
the AFC signal. This AFC voltage is generated in the UEM by an 11 bit D/A converter and tunes
the oscillator.
The AFC voltage is calculated using the values "AFC value" and "AFC slope", which are deter-
mined during Rx calibration of the low band.
mined during Rx calibration of the low band.
The VCO is able to generate frequencies in the range of 3296MHz to 3980MHz. The actual
frequency is controlled by a PLL (Phase locked loop) circuit, which compares the VCO frequen-
cy to the reference frequency from the VCTCXO. The charge pump of the PLL generates pulse
to charge/discharge the capacitors in the loop filter. The output voltage of this filter tunes the
frequency of the VCO.
frequency is controlled by a PLL (Phase locked loop) circuit, which compares the VCO frequen-
cy to the reference frequency from the VCTCXO. The charge pump of the PLL generates pulse
to charge/discharge the capacitors in the loop filter. The output voltage of this filter tunes the
frequency of the VCO.
The valid range of Vc is 0.7V– 3.8V when the PLL is in steady state. The typical tuning sensi-
tivity is 250MHz/V.
tivity is 250MHz/V.