Intel MFS5520VI User Manual
Functional Architecture
Intel® Compute Module MFS5520VI TPS
Revision
1.3
Intel order number: E64311-005
18
3.4.1
PCI Subsystem
The primary I/O buses for the Intel
®
Compute Module MFS5520VI are PCI Express* Gen1 and
PCI Express* Gen2 with six independent PCI bus segments.
PCI Express* Gen1 and Gen2 are dual-simplex point-to point serial differential low-voltage
interconnects. A PCI Express* topology can contain a host bridge and several endpoints (I/O
devices). The signaling bit rate is 2.5 Gbit/s one direction per lane for Gen1 and 5.0 Gbit/s one
direction per lane for Gen2. Each port consists of a transmitter and receiver pair. A link between
the ports of two devices is a collection of lanes (x1, x2, x4, x8, x16, and so on.). All lanes within
a port must transmit data using the same frequency.
interconnects. A PCI Express* topology can contain a host bridge and several endpoints (I/O
devices). The signaling bit rate is 2.5 Gbit/s one direction per lane for Gen1 and 5.0 Gbit/s one
direction per lane for Gen2. Each port consists of a transmitter and receiver pair. A link between
the ports of two devices is a collection of lanes (x1, x2, x4, x8, x16, and so on.). All lanes within
a port must transmit data using the same frequency.
The following table lists the characteristics of the PCI bus segments. Details about each bus
segment are provided in the following table.
segment are provided in the following table.
Table 3. Intel
®
Compute Module MFS5520VI PCI Bus Segment Characteristics
PCI Bus Segment
Voltage
Width
Speed
Type
PCI I/O Card Slots
ESI or DMI Port 0
ICH10R
ICH10R
3.3 V
x4
10 Gb/s
PCI
Express*
Gen1
Express*
Gen1
x4 PCI Express* Gen1 throughput to the
Intel
Intel
®
5520 Chipset IOH
Port 5
ICH10R
ICH10R
3.3 V
x1
2.5 Gb/s
PCI
Express*
Gen1
Express*
Gen1
X1 PCI Express* Gen1 throughput to an
on-board Integrated BMC
on-board Integrated BMC
PE1, PE2
Intel
Intel
®
5520
Chipset IOH PCI
Express*
Express*
3.3 V
x4
10 Gb/s
PCI
Express*
Gen1
Express*
Gen1
x4 PCI Express* Gen1 throughput to the
on-board NIC.
on-board NIC.
PE3, PE4
Intel
Intel
®
5520
Chipset IOH PCI
Express*
Express*
3.3 V
x8
40 Gb/S
PCI
Express*
Gen2
Express*
Gen2
x8 PCI Express* Gen2 throughput – Not
used.
used.
PE5, PE6
Intel
Intel
®
5520
Chipset IOH PCI
Express*
Express*
3.3 V
x8
40 Gb/S
PCI
Express*
Gen2
Express*
Gen2
Two x4 PCI Express* Gen2 throughput -
Not used.
Not used.
PE7, PE8
Intel
Intel
®
5520
Chipset IOH PCI
Express*
Express*
3.3 V
x8
40 Gb/S
PCI
Express*
Gen2
Express*
Gen2
x8 PCI Express* Gen2 throughput to the
on-board LSI 1064E.
on-board LSI 1064E.
PE9, PE10
Intel
Intel
®
5520
Chipset IOH PCI
Express*
Express*
3.3 V
x8
40 Gb/S
PCI
Express*
Gen2
Express*
Gen2
Two x4 PCI Express* Gen2 throughput to
the IO Module Mezzanine connectors.
the IO Module Mezzanine connectors.
3.4.2
USB 2.0 Support
The USB controller functionality integrated into ICH10R provides the Compute Module with an
interface for up to ten USB 2.0 ports. All ports are high-speed, full-speed, and low-speed
capable.
interface for up to ten USB 2.0 ports. All ports are high-speed, full-speed, and low-speed
capable.