Intel 253668-032US User Manual
Vol. 3 2-27
SYSTEM ARCHITECTURE OVERVIEW
state, SSE state, or a future processor extended state) is represented by a bit in
XCR0. The OS can enable future processor extended states in a forward manner by
specifying the appropriate bit mask value using the XSETBV instruction according to
the results of the CPUID leaf 0DH.
With the exception of bit 63, each bit in the XFEATURE_ENABLED_MASK register
(XCR0) corresponds to a subset of the processor states. XCR0 thus provides space
for up to 63 sets of processor state extensions. Bit 63 of XCR0 is reserved for future
expansion and will not represent a processor extended state.
Currently, the XFEATURE_ENABLED_MASK register (XCR0) has two processor states
defined, with up to 61 bits reserved for future processor extended states:
XCR0. The OS can enable future processor extended states in a forward manner by
specifying the appropriate bit mask value using the XSETBV instruction according to
the results of the CPUID leaf 0DH.
With the exception of bit 63, each bit in the XFEATURE_ENABLED_MASK register
(XCR0) corresponds to a subset of the processor states. XCR0 thus provides space
for up to 63 sets of processor state extensions. Bit 63 of XCR0 is reserved for future
expansion and will not represent a processor extended state.
Currently, the XFEATURE_ENABLED_MASK register (XCR0) has two processor states
defined, with up to 61 bits reserved for future processor extended states:
•
XCR0.X87 (bit 0): If 1, indicates x87 FPU state (including MMX register states) is
supported in the processor. Bit 0 must be 1. An attempt to write 0 causes a #GP
exception.
supported in the processor. Bit 0 must be 1. An attempt to write 0 causes a #GP
exception.
•
XCR0.SSE (bit 1): If 1, indicates MXCSR and XMM registers (XMM0-XMM15 in 64-
bit mode, otherwise XMM0-XMM7) are supported by XSAVE/XRESTOR in the
processor.
bit mode, otherwise XMM0-XMM7) are supported by XSAVE/XRESTOR in the
processor.
Any attempt to set a reserved bit (as determined by the contents of EAX and EDX
after executing CPUID with EAX=0DH, ECX= 0H) in the XFEATURE_ENABLED_MASK
register for a given processor will result in a #GP exception. An attempt to write 0 to
XFEATURE_ENABLED_MASK.x87 (bit 0) will result in a #GP exception.
If a bit in the XFEATURE_ENABLED_MASK register is 1, XSAVE instruction can selec-
tively (in conjunction with a save mask) save a partial or full set of processor states
to memory (See XSAVE instruction in Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2B).
After reset all bits (except bit 0) in the XFEATURE_ENABLED_MASK register (XCR0)
are cleared to zero. XCR0[0] is set to 1.
after executing CPUID with EAX=0DH, ECX= 0H) in the XFEATURE_ENABLED_MASK
register for a given processor will result in a #GP exception. An attempt to write 0 to
XFEATURE_ENABLED_MASK.x87 (bit 0) will result in a #GP exception.
If a bit in the XFEATURE_ENABLED_MASK register is 1, XSAVE instruction can selec-
tively (in conjunction with a save mask) save a partial or full set of processor states
to memory (See XSAVE instruction in Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2B).
After reset all bits (except bit 0) in the XFEATURE_ENABLED_MASK register (XCR0)
are cleared to zero. XCR0[0] is set to 1.
2.7 SYSTEM
INSTRUCTION
SUMMARY
System instructions handle system-level functions such as loading system registers,
managing the cache, managing interrupts, or setting up the debug registers. Many of
these instructions can be executed only by operating-system or executive proce-
dures (that is, procedures running at privilege level 0). Others can be executed at
any privilege level and are thus available to application programs.
Table 2-2 lists the system instructions and indicates whether they are available and
useful for application programs. These instructions are described in the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B.
managing the cache, managing interrupts, or setting up the debug registers. Many of
these instructions can be executed only by operating-system or executive proce-
dures (that is, procedures running at privilege level 0). Others can be executed at
any privilege level and are thus available to application programs.
Table 2-2 lists the system instructions and indicates whether they are available and
useful for application programs. These instructions are described in the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B.
Table 2-2. Summary of System Instructions
Instruction
Description
Useful to
Application?
Protected from
Application?
LLDT
Load LDT Register
No
Yes