Intel 253668-032US User Manual
19-26 Vol. 3
ARCHITECTURE COMPATIBILITY
19.22.1.2 Global Pages
The new PGE (page global enable) flag in control register CR4, bit 7, provides a
mechanism for preventing frequently used pages from being flushed from the trans-
lation lookaside buffer (TLB). When this flag is set, frequently used pages (such as
pages containing kernel procedures or common data tables) can be marked global by
setting the global flag in a page-directory or page-table entry.
On a task switch or a write to control register CR3 (which normally causes the TLBs
to be flushed), the entries in the TLB marked global are not flushed. Marking pages
global in this manner prevents unnecessary reloading of the TLB due to TLB misses
on frequently used pages. See Section 4.10, “Caching Translation Information” for a
detailed description of this mechanism.
mechanism for preventing frequently used pages from being flushed from the trans-
lation lookaside buffer (TLB). When this flag is set, frequently used pages (such as
pages containing kernel procedures or common data tables) can be marked global by
setting the global flag in a page-directory or page-table entry.
On a task switch or a write to control register CR3 (which normally causes the TLBs
to be flushed), the entries in the TLB marked global are not flushed. Marking pages
global in this manner prevents unnecessary reloading of the TLB due to TLB misses
on frequently used pages. See Section 4.10, “Caching Translation Information” for a
detailed description of this mechanism.
19.22.1.3 Larger Page Sizes
The P6 family processors support large page sizes. For 32-bit paging, this facility is
enabled with the PSE (page size extension) flag in control register CR4, bit 4. When
this flag is set, the processor supports either 4-KByte or 4-MByte page sizes. PAE
paging and IA-32e paging support 2-MByte pages regardless of the value of CR4.PSE
(see Section 4.4, “PAE Paging” and Section 4.5, “IA-32e Paging”). See Chapter 4,
“Paging,” for more information about large page sizes.
enabled with the PSE (page size extension) flag in control register CR4, bit 4. When
this flag is set, the processor supports either 4-KByte or 4-MByte page sizes. PAE
paging and IA-32e paging support 2-MByte pages regardless of the value of CR4.PSE
(see Section 4.4, “PAE Paging” and Section 4.5, “IA-32e Paging”). See Chapter 4,
“Paging,” for more information about large page sizes.
19.22.2 CD and NW Cache Control Flags
The CD and NW flags in control register CR0 were introduced in the Intel486
processor. In the P6 family and Pentium processors, these flags are used to imple-
ment a writeback strategy for the data cache; in the Intel486 processor, they imple-
ment a write-through strategy. See Table 11-5 for a comparison of these bits on the
P6 family, Pentium, and Intel486 processors. For complete information on caching,
see Chapter 11, “Memory Cache Control.”
processor. In the P6 family and Pentium processors, these flags are used to imple-
ment a writeback strategy for the data cache; in the Intel486 processor, they imple-
ment a write-through strategy. See Table 11-5 for a comparison of these bits on the
P6 family, Pentium, and Intel486 processors. For complete information on caching,
see Chapter 11, “Memory Cache Control.”
19.22.3 Descriptor Types and Contents
Operating-system code that manages space in descriptor tables often contains an
invalid value in the access-rights field of descriptor-table entries to identify unused
entries. Access rights values of 80H and 00H remain invalid for the P6 family,
Pentium, Intel486, Intel386, and Intel 286 processors. Other values that were invalid
on the Intel 286 processor may be valid on the 32-bit processors because uses for
these bits have been defined.
invalid value in the access-rights field of descriptor-table entries to identify unused
entries. Access rights values of 80H and 00H remain invalid for the P6 family,
Pentium, Intel486, Intel386, and Intel 286 processors. Other values that were invalid
on the Intel 286 processor may be valid on the 32-bit processors because uses for
these bits have been defined.