Intel 253668-032US User Manual
Vol. 3 2-15
SYSTEM ARCHITECTURE OVERVIEW
VIP
Virtual interrupt pending (bit 20) — Set by software to indicate that an
interrupt is pending; cleared to indicate that no interrupt is pending. This flag
is used in conjunction with the VIF flag. The processor reads this flag but
never modifies it. The processor only recognizes the VIP flag when either the
VME flag or the PVI flag in control register CR4 is set and the IOPL is less than
3. The VME flag enables the virtual-8086 mode extensions; the PVI flag
enables the protected-mode virtual interrupts.
See Section 17.3.3.5, “Method 6: Software Interrupt Handling,” and Section
17.4, “Protected-Mode Virtual Interrupts.”
interrupt is pending; cleared to indicate that no interrupt is pending. This flag
is used in conjunction with the VIF flag. The processor reads this flag but
never modifies it. The processor only recognizes the VIP flag when either the
VME flag or the PVI flag in control register CR4 is set and the IOPL is less than
3. The VME flag enables the virtual-8086 mode extensions; the PVI flag
enables the protected-mode virtual interrupts.
See Section 17.3.3.5, “Method 6: Software Interrupt Handling,” and Section
17.4, “Protected-Mode Virtual Interrupts.”
ID
Identification (bit 21). — The ability of a program or procedure to set or
clear this flag indicates support for the CPUID instruction.
clear this flag indicates support for the CPUID instruction.
2.3.1
System Flags and Fields in IA-32e Mode
In 64-bit mode, the RFLAGS register expands to 64 bits with the upper 32 bits
reserved. System flags in RFLAGS (64-bit mode) or EFLAGS (compatibility mode)
are shown in Figure 2-4.
In IA-32e mode, the processor does not allow the VM bit to be set because virtual-
8086 mode is not supported (attempts to set the bit are ignored). Also, the processor
will not set the NT bit. The processor does, however, allow software to set the NT bit
(note that an IRET causes a general protection fault in IA-32e mode if the NT bit is
set).
In IA-32e mode, the SYSCALL/SYSRET instructions have a programmable method of
specifying which bits are cleared in RFLAGS/EFLAGS. These instructions save/restore
EFLAGS/RFLAGS.
reserved. System flags in RFLAGS (64-bit mode) or EFLAGS (compatibility mode)
are shown in Figure 2-4.
In IA-32e mode, the processor does not allow the VM bit to be set because virtual-
8086 mode is not supported (attempts to set the bit are ignored). Also, the processor
will not set the NT bit. The processor does, however, allow software to set the NT bit
(note that an IRET causes a general protection fault in IA-32e mode if the NT bit is
set).
In IA-32e mode, the SYSCALL/SYSRET instructions have a programmable method of
specifying which bits are cleared in RFLAGS/EFLAGS. These instructions save/restore
EFLAGS/RFLAGS.
2.4 MEMORY-MANAGEMENT
REGISTERS
The processor provides four memory-management registers (GDTR, LDTR, IDTR,
and TR) that specify the locations of the data structures which control segmented
memory management (see Figure 2-5). Special instructions are provided for loading
and storing these registers.
and TR) that specify the locations of the data structures which control segmented
memory management (see Figure 2-5). Special instructions are provided for loading
and storing these registers.