Intel 253668-032US User Manual
16-32 Vol. 3
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
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The ISR must clear the mask bit in the performance counter LVT entry.
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The ISR must re-enable the counters to count via
IA32_PERF_GLOBAL_CTRL/IA32_PERF_GLOBAL_OVF_CTRL if it is servicing an
overflow PMI due to PEBS (or via CCCR's ENABLE bit on processor based on Intel
NetBurst microarchitecture).
IA32_PERF_GLOBAL_CTRL/IA32_PERF_GLOBAL_OVF_CTRL if it is servicing an
overflow PMI due to PEBS (or via CCCR's ENABLE bit on processor based on Intel
NetBurst microarchitecture).
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The Pentium 4 Processor and Intel Xeon Processor mask PMIs upon receiving an
interrupt. Clear this condition before leaving the interrupt handler.
interrupt. Clear this condition before leaving the interrupt handler.
16.5
LAST BRANCH, INTERRUPT, AND EXCEPTION
RECORDING (INTEL
®
CORE
™
2 DUO AND INTEL
®
ATOM
™
PROCESSOR FAMILY)
The Intel Core 2 Duo processor family and Intel Xeon processors based on Intel Core
microarchitecture or enhanced Intel Core microarchitecture provide last branch
interrupt and exception recording. The facilities described in this section also apply to
Intel Atom processor family. These capabilities are similar to those found in Pentium
4 processors, including support for the following facilities:
microarchitecture or enhanced Intel Core microarchitecture provide last branch
interrupt and exception recording. The facilities described in this section also apply to
Intel Atom processor family. These capabilities are similar to those found in Pentium
4 processors, including support for the following facilities:
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Debug Trace and Branch Recording Control — The IA32_DEBUGCTL MSR
provide bit fields for software to configure mechanisms related to debug trace,
branch recording, branch trace store, and performance counter operations. See
Section 16.4.1 for a description of the flags. See Figure 16-3 for the MSR layout.
provide bit fields for software to configure mechanisms related to debug trace,
branch recording, branch trace store, and performance counter operations. See
Section 16.4.1 for a description of the flags. See Figure 16-3 for the MSR layout.
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Last branch record (LBR) stack — There are a collection of MSR pairs that
store the source and destination addresses related to recently executed
branches. See Section 16.5.1.
store the source and destination addresses related to recently executed
branches. See Section 16.5.1.
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Monitoring and single-stepping of branches, exceptions, and interrupts
— See Section 16.4.2 and Section 16.4.3. In addition, the ability to freeze the
— See Section 16.4.2 and Section 16.4.3. In addition, the ability to freeze the
LBR stack on a PMI request is available.
— The Intel Atom processor family clears the TR flag when the
FREEZE_LBRS_ON_PMI flag is set.
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Branch trace messages — See Section 16.4.4.
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Last exception records — See Section 16.7.3.
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Branch trace store and CPL-qualified BTS — See Section 16.4.5.
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FREEZE_LBRS_ON_PMI flag (bit 11) — see Section 16.4.7.
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FREEZE_PERFMON_ON_PMI flag (bit 12) — see Section 16.4.7.
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FREEZE_WHILE_SMM_EN (bit 14) — FREEZE_WHILE_SMM_EN is supported
if IA32_PERF_CAPABILITIES.FREEZE_WHILE_SMM[Bit 12] is reporting 1. See
Section 16.4.1.
if IA32_PERF_CAPABILITIES.FREEZE_WHILE_SMM[Bit 12] is reporting 1. See
Section 16.4.1.