Intel 253668-032US User Manual
16-28 Vol. 3
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
The procedures used to program IA32_DEBUG_CTRL MSR to set up a BTS buffer or a
CPL-qualified BTS are described in Section 16.4.9.3 and Section 16.4.9.4.
Required elements for writing a DS interrupt service routine are largely the same on
processors that support using DS Save area for BTS or PEBS records. However, on
processors based on Intel NetBurst
CPL-qualified BTS are described in Section 16.4.9.3 and Section 16.4.9.4.
Required elements for writing a DS interrupt service routine are largely the same on
processors that support using DS Save area for BTS or PEBS records. However, on
processors based on Intel NetBurst
®
microarchitecture, re-enabling counting
requires writing to CCCRs. But a DS interrupt service routine on processors based on
Intel Core or Intel Atom microarchitecture should:
Intel Core or Intel Atom microarchitecture should:
•
Re-enable the enable bits in IA32_PERF_GLOBAL_CTRL MSR if it is servicing an
overflow PMI due to PEBS.
overflow PMI due to PEBS.
•
Clear overflow indications by writing to IA32_PERF_GLOBAL_OVF_CTRL when a
counting configuration is changed. This includes bit 62 (ClrOvfBuffer) and the
overflow indication of counters used in either PEBS or general-purpose counting
(specifically: bits 0 or 1; see Figures 30-3).
counting configuration is changed. This includes bit 62 (ClrOvfBuffer) and the
overflow indication of counters used in either PEBS or general-purpose counting
(specifically: bits 0 or 1; see Figures 30-3).
16.4.9.2 Setting Up the DS Save Area
To save branch records with the BTS buffer, the DS save area must first be set up in
memory as described in the following procedure (See Section 30.4.4.1, “Setting up
the PEBS Buffer,” for instructions for setting up a PEBS buffer, respectively, in the DS
save area):
1. Create the DS buffer management information area in memory (see Section
memory as described in the following procedure (See Section 30.4.4.1, “Setting up
the PEBS Buffer,” for instructions for setting up a PEBS buffer, respectively, in the DS
save area):
1. Create the DS buffer management information area in memory (see Section
16.4.9, “BTS and DS Save Area,” and Section 16.4.9.1, “DS Save Area and IA-
32e Mode Operation”). Also see the additional notes in this section.
32e Mode Operation”). Also see the additional notes in this section.
2. Write the base linear address of the DS buffer management area into the
IA32_DS_AREA MSR.
3. Set up the performance counter entry in the xAPIC LVT for fixed delivery and
edge sensitive. See Section 10.6.1, “Local Vector Table.”
4. Establish an interrupt handler in the IDT for the vector associated with the
performance counter entry in the xAPIC LVT.
5. Write an interrupt service routine to handle the interrupt. See Section 16.4.9.5,
The following restrictions should be applied to the DS save area.
•
The three DS save area sections should be allocated from a non-paged pool, and
marked accessed and dirty. It is the responsibility of the operating system to
keep the pages that contain the buffer present and to mark them accessed and
dirty. The implication is that the operating system cannot do “lazy” page-table
entry propagation for these pages.
marked accessed and dirty. It is the responsibility of the operating system to
keep the pages that contain the buffer present and to mark them accessed and
dirty. The implication is that the operating system cannot do “lazy” page-table
entry propagation for these pages.
•
The DS save area can be larger than a page, but the pages must be mapped to
contiguous linear addresses. The buffer may share a page, so it need not be
aligned on a 4-KByte boundary. For performance reasons, the base of the buffer
must be aligned on a doubleword boundary and should be aligned on a cache line
boundary.
contiguous linear addresses. The buffer may share a page, so it need not be
aligned on a 4-KByte boundary. For performance reasons, the base of the buffer
must be aligned on a doubleword boundary and should be aligned on a cache line
boundary.