Intel 253668-032US User Manual
Vol. 3 13-7
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND
— Device not available (#NM). This exception is generated by executing a
SSE/SSE2/SSE3/SSSE3/SSE4 instruction when the TS flag (bit 3) of CR0 is
set to 1.
set to 1.
Other exceptions can occur indirectly due to faulty execution of the above
exceptions.
exceptions.
13.1.6
Providing an Handler for the SIMD Floating-Point Exception
(#XM)
SSE/SSE2/SSE3/SSSE3/SSE4 instructions do not generate numeric exceptions on
packed integer operations. They can generate the following numeric (SIMD floating-
point) exceptions on packed and scalar single-precision and double-precision
floating-point operations.
packed integer operations. They can generate the following numeric (SIMD floating-
point) exceptions on packed and scalar single-precision and double-precision
floating-point operations.
•
Invalid operation (#I)
•
Divide-by-zero (#Z)
•
Denormal operand (#D)
•
Numeric overflow (#O)
•
Numeric underflow (#U)
•
Inexact result (Precision) (#P)
These SIMD floating-point exceptions (with the exception of the denormal operand
exception) are defined in the IEEE Standard 754 for Binary Floating-Point Arithmetic
and represent the same conditions that cause x87 FPU floating-point error excep-
tions (#MF) to be generated for x87 FPU instructions.
Each of these exceptions can be masked, in which case the processor returns a
reasonable result to the destination operand without invoking an exception handler.
However, if any of these exceptions are left unmasked, detection of the exception
condition results in a SIMD floating-point exception (#XM) being generated. See
Chapter 6, “Interrupt 19—SIMD Floating-Point Exception (#XM).”
To handle unmasked SIMD floating-point exceptions, the operating system or execu-
tive must provide an exception handler. The section titled “SSE and SSE2 SIMD
Floating-Point Exceptions” in Chapter 11, “Programming with Streaming SIMD
Extensions 2 (SSE2),” of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1, describes the SIMD floating-point exception classes and gives
suggestions for writing an exception handler to handle them.
To indicate that the operating system provides a handler for SIMD floating-point
exceptions (#XM), the OSXMMEXCPT flag (bit 10) must be set in control register
CR0.
exception) are defined in the IEEE Standard 754 for Binary Floating-Point Arithmetic
and represent the same conditions that cause x87 FPU floating-point error excep-
tions (#MF) to be generated for x87 FPU instructions.
Each of these exceptions can be masked, in which case the processor returns a
reasonable result to the destination operand without invoking an exception handler.
However, if any of these exceptions are left unmasked, detection of the exception
condition results in a SIMD floating-point exception (#XM) being generated. See
Chapter 6, “Interrupt 19—SIMD Floating-Point Exception (#XM).”
To handle unmasked SIMD floating-point exceptions, the operating system or execu-
tive must provide an exception handler. The section titled “SSE and SSE2 SIMD
Floating-Point Exceptions” in Chapter 11, “Programming with Streaming SIMD
Extensions 2 (SSE2),” of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1, describes the SIMD floating-point exception classes and gives
suggestions for writing an exception handler to handle them.
To indicate that the operating system provides a handler for SIMD floating-point
exceptions (#XM), the OSXMMEXCPT flag (bit 10) must be set in control register
CR0.