Intel 253668-032US User Manual
Vol. 3 13-1
CHAPTER 13
SYSTEM PROGRAMMING FOR INSTRUCTION SET
EXTENSIONS AND PROCESSOR EXTENDED STATES
This chapter describes system programming features for instruction set extensions
operating on the processor state extension known as the SSE state (XMM registers,
MXCSR) and for processor extended states. Instruction set extensions operating on
the SSE state include the streaming SIMD extensions (SSE), streaming SIMD exten-
sions 2 (SSE2), streaming SIMD extensions 3 (SSE3), Supplemental SSE3 (SSSE3),
and SSE4.
Sections 13.1 through 13.5 cover system programming requirements to enable
SSE/SSE2/SSE3/SSSE3/SSE4 extensions, providing operating system or executive
support for the SSE/SSE2/SSE3/SSSE3/SSE4 extensions, SIMD floating-point
exceptions, exception handling, and task (context) switching.
Operating system support for SSE state, once implemented using FXSAVE/FXRSTOR,
provides a limited degree of forward support for subsequent instruction set exten-
sions operating on the same known set of processor state. Processor extended states
refer to an extension in Intel 64 architecture that will allow system executives to
implement support for multiple processor state extensions that may be introduced
over time without requiring the system executive to be modified each time a new
processor state extension is introduced.
Managing processor extended states requires the following aspects:
operating on the processor state extension known as the SSE state (XMM registers,
MXCSR) and for processor extended states. Instruction set extensions operating on
the SSE state include the streaming SIMD extensions (SSE), streaming SIMD exten-
sions 2 (SSE2), streaming SIMD extensions 3 (SSE3), Supplemental SSE3 (SSSE3),
and SSE4.
Sections 13.1 through 13.5 cover system programming requirements to enable
SSE/SSE2/SSE3/SSSE3/SSE4 extensions, providing operating system or executive
support for the SSE/SSE2/SSE3/SSSE3/SSE4 extensions, SIMD floating-point
exceptions, exception handling, and task (context) switching.
Operating system support for SSE state, once implemented using FXSAVE/FXRSTOR,
provides a limited degree of forward support for subsequent instruction set exten-
sions operating on the same known set of processor state. Processor extended states
refer to an extension in Intel 64 architecture that will allow system executives to
implement support for multiple processor state extensions that may be introduced
over time without requiring the system executive to be modified each time a new
processor state extension is introduced.
Managing processor extended states requires the following aspects:
•
using instructions like XSAVE, XRSTOR, to save/restore state information to a
memory region consistent with the processor state extensions supported in
hardware,
memory region consistent with the processor state extensions supported in
hardware,
•
using CPUID enumeration features to query the set of extended processor states
supported by the processor,
supported by the processor,
•
using XSETBV instruction to enable individual processor state extensions,
•
maintaining various system programming resources.
System programming for managing processor extended states is described in the
sections starting 13.6.
sections starting 13.6.
13.1
PROVIDING OPERATING SYSTEM SUPPORT FOR
SSE/SSE2/SSE3
/
SSSE3/SSE4 EXTENSIONS
To use SSE/SSE2/SSE3/SSSE3/SSE4 extensions, the operating system or executive
must provide support for initializing the processor to use these extensions, for
handling the FXSAVE and FXRSTOR state saving instructions, and for handling SIMD
floating-point exceptions. The following sections provide system programming
must provide support for initializing the processor to use these extensions, for
handling the FXSAVE and FXRSTOR state saving instructions, and for handling SIMD
floating-point exceptions. The following sections provide system programming