Intel 253668-032US User Manual
11-48 Vol. 3
MEMORY CACHE CONTROL
The requirement that all 4-KByte ranges in a large page are of the same memory
type implies that large pages with different memory types may suffer a performance
penalty, since they must be marked with the lowest common denominator memory
type.
The Pentium 4, Intel Xeon, and P6 family processors provide special support for the
physical memory range from 0 to 4 MBytes, which is potentially mapped by both the
fixed and variable MTRRs. This support is invoked when a Pentium 4, Intel Xeon, or
P6 family processor detects a large page overlapping the first 1 MByte of this
memory range with a memory type that conflicts with the fixed MTRRs. Here, the
processor maps the memory range as multiple 4-KByte pages within the TLB. This
operation insures correct behavior at the cost of performance. To avoid this perfor-
mance penalty, operating-system software should reserve the large page option for
regions of memory at addresses greater than or equal to 4 MBytes.
type implies that large pages with different memory types may suffer a performance
penalty, since they must be marked with the lowest common denominator memory
type.
The Pentium 4, Intel Xeon, and P6 family processors provide special support for the
physical memory range from 0 to 4 MBytes, which is potentially mapped by both the
fixed and variable MTRRs. This support is invoked when a Pentium 4, Intel Xeon, or
P6 family processor detects a large page overlapping the first 1 MByte of this
memory range with a memory type that conflicts with the fixed MTRRs. Here, the
processor maps the memory range as multiple 4-KByte pages within the TLB. This
operation insures correct behavior at the cost of performance. To avoid this perfor-
mance penalty, operating-system software should reserve the large page option for
regions of memory at addresses greater than or equal to 4 MBytes.
11.12 PAGE ATTRIBUTE TABLE (PAT)
The Page Attribute Table (PAT) extends the IA-32 architecture’s page-table format to
allow memory types to be assigned to regions of physical memory based on linear
address mappings. The PAT is a companion feature to the MTRRs; that is, the MTRRs
allow mapping of memory types to regions of the physical address space, where the
PAT allows mapping of memory types to pages within the linear address space. The
MTRRs are useful for statically describing memory types for physical ranges, and are
typically set up by the system BIOS. The PAT extends the functions of the PCD and
PWT bits in page tables to allow all five of the memory types that can be assigned
with the MTRRs (plus one additional memory type) to also be assigned dynamically
to pages of the linear address space.
The PAT was introduced to IA-32 architecture on the Pentium III processor. It is also
available in the Pentium 4 and Intel Xeon processors.
allow memory types to be assigned to regions of physical memory based on linear
address mappings. The PAT is a companion feature to the MTRRs; that is, the MTRRs
allow mapping of memory types to regions of the physical address space, where the
PAT allows mapping of memory types to pages within the linear address space. The
MTRRs are useful for statically describing memory types for physical ranges, and are
typically set up by the system BIOS. The PAT extends the functions of the PCD and
PWT bits in page tables to allow all five of the memory types that can be assigned
with the MTRRs (plus one additional memory type) to also be assigned dynamically
to pages of the linear address space.
The PAT was introduced to IA-32 architecture on the Pentium III processor. It is also
available in the Pentium 4 and Intel Xeon processors.
11.12.1 Detecting Support for the PAT Feature
An operating system or executive can detect the availability of the PAT by executing
the CPUID instruction with a value of 1 in the EAX register. Support for the PAT is indi-
cated by the PAT flag (bit 16 of the values returned to EDX register). If the PAT is
supported, the operating system or executive can use the IA32_PAT MSR to program
the PAT. When memory types have been assigned to entries in the PAT, software can
then use of the PAT-index bit (PAT) in the page-table and page-directory entries
along with the PCD and PWT bits to assign memory types from the PAT to individual
pages.
Note that there is no separate flag or control bit in any of the control registers that
enables the PAT. The PAT is always enabled on all processors that support it, and the
table lookup always occurs whenever paging is enabled, in all paging modes.
the CPUID instruction with a value of 1 in the EAX register. Support for the PAT is indi-
cated by the PAT flag (bit 16 of the values returned to EDX register). If the PAT is
supported, the operating system or executive can use the IA32_PAT MSR to program
the PAT. When memory types have been assigned to entries in the PAT, software can
then use of the PAT-index bit (PAT) in the page-table and page-directory entries
along with the PCD and PWT bits to assign memory types from the PAT to individual
pages.
Note that there is no separate flag or control bit in any of the control registers that
enables the PAT. The PAT is always enabled on all processors that support it, and the
table lookup always occurs whenever paging is enabled, in all paging modes.