Intel 253668-032US User Manual
Vol. 3 11-41
MEMORY CACHE CONTROL
11.11.4 Range Size and Alignment Requirement
A range that is to be mapped to a variable-range MTRR must meet the following
“power of 2” size and alignment rules:
1. The minimum range size is 4 KBytes and the base address of the range must be
“power of 2” size and alignment rules:
1. The minimum range size is 4 KBytes and the base address of the range must be
on at least a 4-KByte boundary.
2. For ranges greater than 4 KBytes, each range must be of length 2
n
and its base
address must be aligned on a 2
n
boundary, where n is a value equal to or greater
than 12. The base-address alignment value cannot be less than its length. For
example, an 8-KByte range cannot be aligned on a 4-KByte boundary. It must be
aligned on at least an 8-KByte boundary.
example, an 8-KByte range cannot be aligned on a 4-KByte boundary. It must be
aligned on at least an 8-KByte boundary.
11.11.4.1 MTRR Precedences
If the MTRRs are not enabled (by setting the E flag in the IA32_MTRR_DEF_TYPE
MSR), then all memory accesses are of the UC memory type. If the MTRRs are
enabled, then the memory type used for a memory access is determined as follows:
1. If the physical address falls within the first 1 MByte of physical memory and
MSR), then all memory accesses are of the UC memory type. If the MTRRs are
enabled, then the memory type used for a memory access is determined as follows:
1. If the physical address falls within the first 1 MByte of physical memory and
fixed MTRRs are enabled, the processor uses the memory type stored for the
appropriate fixed-range MTRR.
appropriate fixed-range MTRR.
2. Otherwise, the processor attempts to match the physical address with a memory
type set by the variable-range MTRRs:
— If one variable memory range matches, the processor uses the memory type
— If one variable memory range matches, the processor uses the memory type
stored in the IA32_MTRR_PHYSBASEn register for that range.
— If two or more variable memory ranges match and the memory types are
identical, then that memory type is used.
— If two or more variable memory ranges match and one of the memory types
is UC, the UC memory type used.
— If two or more variable memory ranges match and the memory types are WT
and WB, the WT memory type is used.
— For overlaps not defined by the above rules, processor behavior is undefined.
3. If no fixed or variable memory range matches, the processor uses the default
memory type.
11.11.5 MTRR
Initialization
On a hardware reset, the P6 and more recent processors clear the valid flags in vari-
able-range MTRRs and clear the E flag in the IA32_MTRR_DEF_TYPE MSR to disable
all MTRRs. All other bits in the MTRRs are undefined.
Prior to initializing the MTRRs, software (normally the system BIOS) must initialize all
fixed-range and variable-range MTRR register fields to 0. Software can then initialize
able-range MTRRs and clear the E flag in the IA32_MTRR_DEF_TYPE MSR to disable
all MTRRs. All other bits in the MTRRs are undefined.
Prior to initializing the MTRRs, software (normally the system BIOS) must initialize all
fixed-range and variable-range MTRR register fields to 0. Software can then initialize