Intel 253668-032US User Manual
Vol. 3 10-65
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
the bus regardless of its sender’s arbitration priority, unless more than one APIC
issues an EOI message simultaneously. In the latter case, the APICs sending the EOI
messages arbitrate using their arbitration priorities.
If the APICs are set up to use “lowest priority” arbitration (see
issues an EOI message simultaneously. In the latter case, the APICs sending the EOI
messages arbitrate using their arbitration priorities.
If the APICs are set up to use “lowest priority” arbitration (see
) and multiple APICs are currently executing at the
lowest priority (the value in the APR register), the arbitration priorities (unique
values in the Arb ID register) are used to break ties. All 8 bits of the APR are used for
the lowest priority arbitration.
values in the Arb ID register) are used to break ties. All 8 bits of the APR are used for
the lowest priority arbitration.
10.11.1 Bus Message Formats
See Appendix F, “APIC Bus Message Formats,” for a description of bus message
formats used to transmit messages on the serial APIC bus.
formats used to transmit messages on the serial APIC bus.
10.12 MESSAGE SIGNALLED INTERRUPTS
The PCI Local Bus Specification, Rev 2.2 (www.pcisig.com) introduces the concept of
message signalled interrupts. Intel processors and chipsets with this capability
currently include the Pentium 4 and Intel Xeon processors. As the specification indi-
cates:
message signalled interrupts. Intel processors and chipsets with this capability
currently include the Pentium 4 and Intel Xeon processors. As the specification indi-
cates:
“Message signalled interrupts (MSI) is an optional feature that
enables PCI devices to request service by writing a system-specified
message to a system-specified address (PCI DWORD memory write
transaction). The transaction address specifies the message
destination while the transaction data specifies the message. System
software is expected to initialize the message destination and
message during device configuration, allocating one or more non-
shared messages to each MSI capable function.”
enables PCI devices to request service by writing a system-specified
message to a system-specified address (PCI DWORD memory write
transaction). The transaction address specifies the message
destination while the transaction data specifies the message. System
software is expected to initialize the message destination and
message during device configuration, allocating one or more non-
shared messages to each MSI capable function.”
The capabilities mechanism provided by the PCI Local Bus Specification is used to
identify and configure MSI capable PCI devices. Among other fields, this structure
contains a Message Data Register and a Message Address Register. To request
service, the PCI device function writes the contents of the Message Data Register to
the address contained in the Message Address Register (and the Message Upper
Address register for 64-bit message addresses).
identify and configure MSI capable PCI devices. Among other fields, this structure
contains a Message Data Register and a Message Address Register. To request
service, the PCI device function writes the contents of the Message Data Register to
the address contained in the Message Address Register (and the Message Upper
Address register for 64-bit message addresses).
and
provide layout details for the Message Address
Register and the Message Data Register. The operation issued by the device is a PCI
write command to the Message Address Register with the Message Data Register
contents. The operation follows semantic rules as defined for PCI write operations
and is a DWORD operation.
write command to the Message Address Register with the Message Data Register
contents. The operation follows semantic rules as defined for PCI write operations
and is a DWORD operation.