Intel 253668-032US User Manual
10-22 Vol. 3
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
to enable BIOS and/or platform firmware to re-configure the x2APIC IDs in some
clusters to provide for unique and non-overlapping system wide IDs before config-
uring the disconnected components into a single system.
clusters to provide for unique and non-overlapping system wide IDs before config-
uring the disconnected components into a single system.
10.5.2
x2APIC Register Availability
The local APIC registers can be accessed via the MSR interface only when the local
APIC has been switched to the x2APIC mode as described in
APIC has been switched to the x2APIC mode as described in
Accessing any APIC register in the MSR address range 0800H through 0BFFH via
RDMSR or WRMSR when the local APIC is not in x2APIC mode will cause the instruc-
tions to raise a GP fault. In x2APIC mode, the memory mapped interface is not avail-
able and any access to the MMIO interface will behave similar to that of a legacy
xAPIC in globally disabled state.
RDMSR or WRMSR when the local APIC is not in x2APIC mode will cause the instruc-
tions to raise a GP fault. In x2APIC mode, the memory mapped interface is not avail-
able and any access to the MMIO interface will behave similar to that of a legacy
xAPIC in globally disabled state.
legacy & extended modes and the legacy and register interfaces.
10.5.3
MSR Access in x2APIC Mode
To allow for efficient access to the APIC registers in x2APIC mode, the serializing
semantics of WRMSR are relaxed when writing to the APIC registers. Thus, system
software should not use “WRMSR to APIC registers in x2APIC mode” as a serializing
instruction. Read and write accesses to the APIC registers will occur in program
order. A WRMSR to an APIC register may complete before all preceding stores are
globally visible; software can prevent this by inserting a serializing instruction or
MFENCE before the WRMSR.
The RDMSR instruction is not serializing and this behavior is unchanged when
reading APIC registers in x2APIC mode. System software accessing the APIC regis-
ters using the RDMSR instruction should not expect a serializing behavior. (Note: The
MMIO-based xAPIC interface is mapped by system software as an un-cached region.
Consequently, read/writes to the xAPIC-MMIO interface have serializing semantics in
the xAPIC mode.)
semantics of WRMSR are relaxed when writing to the APIC registers. Thus, system
software should not use “WRMSR to APIC registers in x2APIC mode” as a serializing
instruction. Read and write accesses to the APIC registers will occur in program
order. A WRMSR to an APIC register may complete before all preceding stores are
globally visible; software can prevent this by inserting a serializing instruction or
MFENCE before the WRMSR.
The RDMSR instruction is not serializing and this behavior is unchanged when
reading APIC registers in x2APIC mode. System software accessing the APIC regis-
ters using the RDMSR instruction should not expect a serializing behavior. (Note: The
MMIO-based xAPIC interface is mapped by system software as an un-cached region.
Consequently, read/writes to the xAPIC-MMIO interface have serializing semantics in
the xAPIC mode.)
10.5.4
VM-exit Controls for MSRs and x2APIC Registers
The VMX architecture allows a VMM to specify lists of MSRs to be loaded or stored on
VMX transitions using the VMX-transition MSR areas (see VM-exit MSR-store address
VMX transitions using the VMX-transition MSR areas (see VM-exit MSR-store address
Table 10-4. MSR/MMIO Interface of a Local x2APIC in Different Modes of Operation
MMIO Interface
MSR Interface
xAPIC mode
Available
GP Fault
x2APIC mode
Behavior identical to xAPIC in globally
disabled state
Available