Intel 253668-032US User Manual
8-44 Vol. 3
MULTIPLE-PROCESSOR MANAGEMENT
As a consequence, the use of the WBINVD instruction can have an impact on
interrupt/event response time.
interrupt/event response time.
•
INVD instruction — The entire cache hierarchy is invalidated without writing
back modified data to memory. All logical processors are stopped from executing
until after the invalidate operation is completed. A special bus cycle is sent to all
caching agents.
back modified data to memory. All logical processors are stopped from executing
until after the invalidate operation is completed. A special bus cycle is sent to all
caching agents.
•
CLFLUSH instruction — The specified cache line is invalidated from the cache
hierarchy after any modified data is written back to memory and a bus cycle is
sent to all caching agents, regardless of which logical processor caused the cache
line to be filled.
hierarchy after any modified data is written back to memory and a bus cycle is
sent to all caching agents, regardless of which logical processor caused the cache
line to be filled.
•
CD flag in control register CR0 — Each logical processor has its own CR0
control register, and thus its own CD flag in CR0. The CD flags for the two logical
processors are ORed together, such that when any logical processor sets its CD
flag, the entire cache is nominally disabled.
control register, and thus its own CD flag in CR0. The CD flags for the two logical
processors are ORed together, such that when any logical processor sets its CD
flag, the entire cache is nominally disabled.
8.7.13.2 Processor Translation Lookaside Buffers (TLBs)
In processors supporting Intel Hyper-Threading Technology, data cache TLBs are
shared. The instruction cache TLB may be duplicated or shared in each logical
processor, depending on implementation specifics of different processor families.
Entries in the TLBs are tagged with an ID that indicates the logical processor that
initiated the translation. This tag applies even for translations that are marked global
using the page-global feature for memory paging. See Section 4.10, “Caching Trans-
lation Information,” for information about global translations.
When a logical processor performs a TLB invalidation operation, only the TLB entries
that are tagged for that logical processor are guaranteed to be flushed. This protocol
applies to all TLB invalidation operations, including writes to control registers CR3
and CR4 and uses of the INVLPG instruction.
shared. The instruction cache TLB may be duplicated or shared in each logical
processor, depending on implementation specifics of different processor families.
Entries in the TLBs are tagged with an ID that indicates the logical processor that
initiated the translation. This tag applies even for translations that are marked global
using the page-global feature for memory paging. See Section 4.10, “Caching Trans-
lation Information,” for information about global translations.
When a logical processor performs a TLB invalidation operation, only the TLB entries
that are tagged for that logical processor are guaranteed to be flushed. This protocol
applies to all TLB invalidation operations, including writes to control registers CR3
and CR4 and uses of the INVLPG instruction.
8.7.13.3 Thermal Monitor
In a processor that supports Intel Hyper-Threading Technology, logical processors
share the catastrophic shutdown detector and the automatic thermal monitoring
mechanism (see Section 14.5, “Thermal Monitoring and Protection”). Sharing results
in the following behavior:
share the catastrophic shutdown detector and the automatic thermal monitoring
mechanism (see Section 14.5, “Thermal Monitoring and Protection”). Sharing results
in the following behavior:
•
If the processor’s core temperature rises above the preset catastrophic shutdown
temperature, the processor core halts execution, which causes both logical
processors to stop execution.
temperature, the processor core halts execution, which causes both logical
processors to stop execution.
•
When the processor’s core temperature rises above the preset automatic thermal
monitor trip temperature, the clock speed of the processor core is automatically
modulated, which effects the execution speed of both logical processors.
monitor trip temperature, the clock speed of the processor core is automatically
modulated, which effects the execution speed of both logical processors.
For software controlled clock modulation, each logical processor has its own
IA32_CLOCK_MODULATION MSR, allowing clock modulation to be enabled or
IA32_CLOCK_MODULATION MSR, allowing clock modulation to be enabled or