Intel 253668-032US User Manual
Vol. 3 8-27
MULTIPLE-PROCESSOR MANAGEMENT
8.4.1
BSP and AP Processors
The MP initialization protocol defines two classes of processors: the bootstrap
processor (BSP) and the application processors (APs). Following a power-up or
RESET of an MP system, system hardware dynamically selects one of the processors
on the system bus as the BSP. The remaining processors are designated as APs.
As part of the BSP selection mechanism, the BSP flag is set in the IA32_APIC_BASE
MSR (see Figure 10-5) of the BSP, indicating that it is the BSP. This flag is cleared for
all other processors.
The BSP executes the BIOS’s boot-strap code to configure the APIC environment,
sets up system-wide data structures, and starts and initializes the APs. When the BSP
and APs are initialized, the BSP then begins executing the operating-system initial-
ization code.
Following a power-up or reset, the APs complete a minimal self-configuration, then
wait for a startup signal (a SIPI message) from the BSP processor. Upon receiving a
SIPI message, an AP executes the BIOS AP configuration code, which ends with the
AP being placed in halt state.
For Intel 64 and IA-32 processors supporting Intel Hyper-Threading Technology, the
MP initialization protocol treats each of the logical processors on the system bus or
coherent link domain as a separate processor (with a unique APIC ID). During boot-
up, one of the logical processors is selected as the BSP and the remainder of the
logical processors are designated as APs.
processor (BSP) and the application processors (APs). Following a power-up or
RESET of an MP system, system hardware dynamically selects one of the processors
on the system bus as the BSP. The remaining processors are designated as APs.
As part of the BSP selection mechanism, the BSP flag is set in the IA32_APIC_BASE
MSR (see Figure 10-5) of the BSP, indicating that it is the BSP. This flag is cleared for
all other processors.
The BSP executes the BIOS’s boot-strap code to configure the APIC environment,
sets up system-wide data structures, and starts and initializes the APs. When the BSP
and APs are initialized, the BSP then begins executing the operating-system initial-
ization code.
Following a power-up or reset, the APs complete a minimal self-configuration, then
wait for a startup signal (a SIPI message) from the BSP processor. Upon receiving a
SIPI message, an AP executes the BIOS AP configuration code, which ends with the
AP being placed in halt state.
For Intel 64 and IA-32 processors supporting Intel Hyper-Threading Technology, the
MP initialization protocol treats each of the logical processors on the system bus or
coherent link domain as a separate processor (with a unique APIC ID). During boot-
up, one of the logical processors is selected as the BSP and the remainder of the
logical processors are designated as APs.
8.4.2
MP Initialization Protocol Requirements and Restrictions
The MP initialization protocol imposes the following requirements and restrictions on
the system:
the system:
•
The MP protocol is executed only after a power-up or RESET. If the MP protocol
has completed and a BSP is chosen, subsequent INITs (either to a specific
processor or system wide) do not cause the MP protocol to be repeated. Instead,
each logical processor examines its BSP flag (in the IA32_APIC_BASE MSR) to
determine whether it should execute the BIOS boot-strap code (if it is the BSP) or
enter a wait-for-SIPI state (if it is an AP).
has completed and a BSP is chosen, subsequent INITs (either to a specific
processor or system wide) do not cause the MP protocol to be repeated. Instead,
each logical processor examines its BSP flag (in the IA32_APIC_BASE MSR) to
determine whether it should execute the BIOS boot-strap code (if it is the BSP) or
enter a wait-for-SIPI state (if it is an AP).
•
All devices in the system that are capable of delivering interrupts to the
processors must be inhibited from doing so for the duration of the MP initial-
ization protocol. The time during which interrupts must be inhibited includes the
window between when the BSP issues an INIT-SIPI-SIPI sequence to an AP and
when the AP responds to the last SIPI in the sequence.
processors must be inhibited from doing so for the duration of the MP initial-
ization protocol. The time during which interrupts must be inhibited includes the
window between when the BSP issues an INIT-SIPI-SIPI sequence to an AP and
when the AP responds to the last SIPI in the sequence.