Intel 253668-032US User Manual
Vol. 3 7-21
TASK MANAGEMENT
shared LDT point to segments that are mapped to a common area of the physical
address space, the data and code in those segments can be shared among the
tasks that share the LDT. This method of sharing is more selective than sharing
through the GDT, because the sharing can be limited to specific tasks. Other
tasks in the system may have different LDTs that do not give them access to the
shared segments.
address space, the data and code in those segments can be shared among the
tasks that share the LDT. This method of sharing is more selective than sharing
through the GDT, because the sharing can be limited to specific tasks. Other
tasks in the system may have different LDTs that do not give them access to the
shared segments.
•
Through segment descriptors in distinct LDTs that are mapped to
common addresses in linear address space — If this common area of the
linear address space is mapped to the same area of the physical address space
for each task, these segment descriptors permit the tasks to share segments.
Such segment descriptors are commonly called aliases. This method of sharing is
even more selective than those listed above, because, other segment descriptors
in the LDTs may point to independent linear addresses which are not shared.
common addresses in linear address space — If this common area of the
linear address space is mapped to the same area of the physical address space
for each task, these segment descriptors permit the tasks to share segments.
Such segment descriptors are commonly called aliases. This method of sharing is
even more selective than those listed above, because, other segment descriptors
in the LDTs may point to independent linear addresses which are not shared.
7.6
16-BIT TASK-STATE SEGMENT (TSS)
The 32-bit IA-32 processors also recognize a 16-bit TSS format like the one used in
Intel 286 processors (see Figure 7-10). This format is supported for compatibility
with software written to run on earlier IA-32 processors.
The following information is important to know about the 16-bit TSS.
Intel 286 processors (see Figure 7-10). This format is supported for compatibility
with software written to run on earlier IA-32 processors.
The following information is important to know about the 16-bit TSS.
•
Do not use a 16-bit TSS to implement a virtual-8086 task.
•
The valid segment limit for a 16-bit TSS is 2CH.
•
The 16-bit TSS does not contain a field for the base address of the page directory,
which is loaded into control register CR3. A separate set of page tables for each
task is not supported for 16-bit tasks. If a 16-bit task is dispatched, the page-
table structure for the previous task is used.
which is loaded into control register CR3. A separate set of page tables for each
task is not supported for 16-bit tasks. If a 16-bit task is dispatched, the page-
table structure for the previous task is used.
•
The I/O base address is not included in the 16-bit TSS. None of the functions of
the I/O map are supported.
the I/O map are supported.
•
When task state is saved in a 16-bit TSS, the upper 16 bits of the EFLAGS register
and the EIP register are lost.
and the EIP register are lost.
•
When the general-purpose registers are loaded or saved from a 16-bit TSS, the
upper 16 bits of the registers are modified and not maintained.
upper 16 bits of the registers are modified and not maintained.