Intel 253668-032US User Manual
4-40 Vol. 3
PAGING
4.10.1.2 Caching Translations in TLBs
The processor may accelerate the paging process by caching individual translations
in translation lookaside buffers (TLBs). Each entry in a TLB is an individual trans-
lation. Each translation is referenced by a page number. It contains the following
information from the paging-structure entries used to translate linear addresses with
the page number:
in translation lookaside buffers (TLBs). Each entry in a TLB is an individual trans-
lation. Each translation is referenced by a page number. It contains the following
information from the paging-structure entries used to translate linear addresses with
the page number:
•
The physical address corresponding to the page number (the page frame).
•
The access rights from the paging-structure entries used to translate linear
addresses with the page number (see Section 4.6):
— The logical-AND of the R/W flags.
— The logical-AND of the U/S flags.
— The logical-OR of the XD flags (necessary only if IA32_EFER.NXE = 1).
addresses with the page number (see Section 4.6):
— The logical-AND of the R/W flags.
— The logical-AND of the U/S flags.
— The logical-OR of the XD flags (necessary only if IA32_EFER.NXE = 1).
•
Attributes from a paging-structure entry that identifies the final page frame for
the page number (either a PTE or a PDE in which the PS flag is 1):
— The dirty flag (see Section 4.8).
— The memory type (see Section 4.9).
the page number (either a PTE or a PDE in which the PS flag is 1):
— The dirty flag (see Section 4.8).
— The memory type (see Section 4.9).
(TLB entries may contain other information as well. A processor may implement
multiple TLBs, and some of these may be for special purposes, e.g., only for instruc-
tion fetches. Such special-purpose TLBs may not contain some of this information if
it is not necessary. For example, a TLB used only for instruction fetches need not
contain information about the R/W and dirty flags.)
Processors need not implement any TLBs. Processors that do implement TLBs may
invalidate any TLB entry at any time. Software should not rely on the existence of
TLBs or on the retention of TLB entries.
multiple TLBs, and some of these may be for special purposes, e.g., only for instruc-
tion fetches. Such special-purpose TLBs may not contain some of this information if
it is not necessary. For example, a TLB used only for instruction fetches need not
contain information about the R/W and dirty flags.)
Processors need not implement any TLBs. Processors that do implement TLBs may
invalidate any TLB entry at any time. Software should not rely on the existence of
TLBs or on the retention of TLB entries.
4.10.1.3 Details of TLB Use
Because the TLBs cache only valid translations, there can be a TLB entry for a page
number only if the P flag is 1 and the reserved bits are 0 in each of the paging-struc-
ture entries used to translate that page number. In addition, the processor does not
cache a translation for a page number unless the accessed flag is 1 in each of the
paging-structure entries used during translation; before caching a translation, the
processor sets any of these accessed flags that is not already 1.
The processor may cache translations required for prefetches and for accesses that
are a result of speculative execution that would never actually occur in the executed
code path.
If the page number of a linear address corresponds to a TLB entry, the processor may
use that TLB entry to determine the page frame, access rights, and other attributes
for accesses to that linear address. In this case, the processor may not actually
consult the paging structures in memory. The processor may retain a TLB entry
unmodified even if software subsequently modifies the relevant paging-structure
number only if the P flag is 1 and the reserved bits are 0 in each of the paging-struc-
ture entries used to translate that page number. In addition, the processor does not
cache a translation for a page number unless the accessed flag is 1 in each of the
paging-structure entries used during translation; before caching a translation, the
processor sets any of these accessed flags that is not already 1.
The processor may cache translations required for prefetches and for accesses that
are a result of speculative execution that would never actually occur in the executed
code path.
If the page number of a linear address corresponds to a TLB entry, the processor may
use that TLB entry to determine the page frame, access rights, and other attributes
for accesses to that linear address. In this case, the processor may not actually
consult the paging structures in memory. The processor may retain a TLB entry
unmodified even if software subsequently modifies the relevant paging-structure