Intel 249323-003 User Manual
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion
Development Kit Manual
33
Document #: 249323
Revision #: 003
Rev. Date: January 24, 2002
Revision #: 003
Rev. Date: January 24, 2002
Figure 18. Logic Analyzer
A
A
B
B
C
C
D
D
E
E
4
4
3
3
2
2
1
1
L
O
G
I
C
A
N
A
LY
Z
E
R
P
O
R
T
S
0-
3
L
O
G
I
C
A
N
A
LY
Z
E
R
P
O
R
T
S
4-
7
LOGIC ANALYZER CONNECTOR'S
A
2
L
X
D
97
85
S
S
/S
M
II
M
II
F
X
D
V
B
O
A
R
D
B
16
18
Wednesday, February 21, 2001
Title
Size
Document Number
R
ev
Date:
S
he
et
of
TX
D_P5
RXD_
P
5
RXD_
P
4
TX
D_P4
RXD_
P
6
TX
D_P6
TX
D_P7
RXD_
P
7
TX
D_P1
TX
D_P2
TX
D_P3
TX
D_P4
TX
D_P5
TX
D_P6
TX
D_P7
TX
D_P0
RXD_
P
0
RXD_
P
1
RXD_
P
2
RXD_
P
3
RXD_
P
4
RXD_
P
5
RXD_
P
6
RXD_
P
7
T
X
_CLK0
TX_SYNC0
RX_SYNC
RX_C
LK
TX
D_P1
RXD_
P
0
RXD_
P
2
TX
D_P3
RXD_
P
1
RX_C
LK
TX_SYNC0
T
X
_CLK0
TX
D_P0
TX
D_P2
RX_SYNC
RXD_
P
3
RX_C
LK
1
TX_SYNC1
T
X
_CLK1
RX_SYNC1
T
X
_CLK1
TX_SYNC1
RX_SYNC1
RX_C
LK
1
RXD_
P
0
4
RXD_
P
1
4
RXD_
P
2
5
RXD_
P
3
5
RXD_
P
4
6
RXD_
P
5
6
RXD_
P
6
7
RXD_
P
7
7
TX
D_P0
4
TX
D_P1
4
TX
D_P2
5
TX
D_P3
5
TX
D_P4
6
TX
D_P5
6
TX
D_P6
7
TX
D_P7
7
TX_SYNC0
3,13
T
X
_CLK0
3,13
RX_SYNC
3,13
RX_C
LK
3,13
TX_SYNC1
3,13
T
X
_CLK1
3,13
RX_SYNC1
3,13
RX_C
LK
1
3,13
GND
U9
MICTOR PROBE
2
37
38
1
3
36
11
10
9
8
7
6
5
4
19
18
17
16
15
14
13
12
28
29
30
31
32
33
34
35
20
21
22
23
24
25
26
27
39
40
42
41
41
43
N/C
N/C
N/C
N/C
CLK
N
/C
N/C
RXD1
TXD1
N/C
RXD0
TXD0
N/C
N/C
N/C
N/C
N/C
RXD3
TXD3
N/C
RXD2
TXD2
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
MDC
MDIO
N/C
SYNC
N/C
N/C
N/C
N/C
GND
GND
GND
GND
GND
GND
U10
MICTOR PROBE
2
37
38
1
3
36
11
10
9
8
7
6
5
4
19
18
17
16
15
14
13
12
28
29
30
31
32
33
34
35
20
21
22
23
24
25
26
27
39
40
42
41
41
43
N/C
N/C
N/C
N/C
CLK
N
/C
N/C
RXD1
TXD1
N/C
RXD0
TXD0
N/C
N/C
N/C
N/C
N/C
RXD3
TXD3
N/C
RXD2
TXD2
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
MDC
MDIO
N/C
SYNC
N/C
N/C
N/C
N/C
GND
GND
GND
GND
GND
GND