Intel 249323-003 User Manual
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion
20
Development Kit Manual
Document #: 249323
Revision #: 003
Rev. Date: January 24, 2002
Figure 5. Control
A
A
B
B
C
C
D
D
E
E
4
4
3
3
2
2
1
1
IN
IN
MDINT
J
T
A
G
PO
R
T
2
X
4
M
O
D
E
1
X
8
M
O
D
E
R
E
M
O
V
E
J
P1
2
F
O
R
3
.
3
V
S
D
I
N
T
E
R
F
A
CE
CONTROL
A
2
L
X
D
97
85
S
S
/S
M
II
M
II
F
X
D
V
B
O
A
R
D
B
31
8
Wednesday, February 21, 2001
Title
Size
Document Number
R
ev
D
at
e:
Sheet
of
MDC1_FIX
MDC0_FIX
TDI
REF_CLK_0
REF_CLK_1
TMS
TCK
TDO
TX_SYNC0
MDIO0_1
MDC0_1
MDIO1_1
MDC1_1
MDDIS
nRESET
TRST
ADD_0
MDIO1_FIX
MDIO1
TRST
TMS
ADD_1
TFIFO
MDINT1
MODES
EL_1
TCK
TSLE
W
_0
ADD_3
PWRDWN
MDIO0_FI
X
ADD_4
MDC0
TSLE
W
_1
MDC1
TDO
MDIO0
MDINT0
REF_CLK_0
ADD_2
REF_CLK_1
PAUSE
TDI
AMDIX_E
N
TX_C
LK
0
RX_SYNC0
RX_C
LK
0
MDIX
SECTION
TX_C
LK
1
RX_C
LK
0
RX_SYNC
RX_C
LK
1
RX_SYNC0
RX_SYNC1
RX_C
LK
TX_SYNC1
SECTION
SD_2P5V
SD_2P5
V
SECTION
CFG_1
CFG_2
CFG_3
MODES
EL_0
MDIO0_1
MDIO1_1
RX_SYNC
RX_CL
K
nRESET
RX_SYNC1
RX_CL
K
1
MDC1_FIX
MDC0_FIX
MDIO0_FIX
MDIO1_FIX
SECTION
MDC0_1
MDC1_1
TX_SYNC0
TX
_CLK0
TX_SYNC1
TX
_CLK1
MDC0
MDC1
MDIO0
MDIO1
RX_SYNC1
RX_CL
K
1
REF_CLK_0
14
REF_CLK_1
14
MDIO0_1
4
MDIO1_1
6
RX_C
LK
13,16
RX_SYNC
13
,1
6
nRESET
13
RX_C
LK
1
13,16
RX_SYNC1
13
,1
6
MDIO1_FIX
18
MDIO0_FIX
17
MDC0_FIX
17
MDC1_FIX
18
SECTION
14
MDC0_1
4
MDC1_1
6
TX
_CLK0
13,16
TX_SYNC0
13,16
TX
_CLK1
13,16
TX_SYNC1
13,16
MDC0
17
MDC1
18
MDIO0
17
MDIO1
18
GND
GND
GND
GND
GND
GND
GND
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
GND
VCCIO
GND
VCC_PECL
GND
VCCIO
GND
VCCIO
JP19
R21
4.7K
U1L
LXT9785_
S
S
/S
M
II
60
58
17
21
35
201
204
32
RX_CLK0(SS)
RX_SYNC0(SS)
RX_SYNC1(SS)
RX_CLK1(SS)
TXSYNC0(SS)
TX_CLK1(SS)
TXSYNC1(SS)
TX_CLK0(SS)
J2
RJ11
1
2
3
4
5
6
R23
10K
R558
45.3
TP
1
1
R568
30.1 1%
D
1
LED RD
R569
30.1 1%
R
6
4.7K
R12
22
0
S4
SW-NO
2
1
3
J3
RJ11
1
2
3
4
5
6
TP
5
1
R559
45.3
JP1
HEADER 3X1
1
2
3
+
C1
10uF
R11
10
0
JP4
HEADER 3X1
1
2
3
D2
LL41
48
JP5
HEADER 3X1
1
2
3
R5
4.7K
S5
SW DIP-4
1
2
3
4
8
7
6
5
JP2
HEADER 3X1
1
2
3
R4
4.7K
R10
4.7K
U2F
74HC14
13
12
R3
4.7K
JP12
U2A
74HC14
1
2
U2E
74HC14
11
10
R725
4.7K
U2C
74HC14
5
6
R14
4.7K
S1
SW DIP-5
1
2
3
4
5
10
9
8
7
6
U2D
74HC14
9
8
JP15
HEADER 3X1
1
2
3
R16
4.7K
R8
4.7K
D155
LED
TP
2
1
R7
4.7K
D156
LED
R15
4.7K
R26
4.7K
R610
22
0
R25
4.7K
U1I
LXT9785_
S
S
/S
M
II
63
64
94
93
50
174
175
67
84
6
92
91
90
89
88
167
168
169
170
171
44
24
25
26
177
178
176
83
59
87
86
85
173
172
95
MDC0
MDIO0
TxSLEW_0
TxSLEW_1
PAUSE
PWRDWN
RESET
MDINT0
MDDIS
REFCLK1
ADD_0
ADD_1
ADD_2
ADD_3
ADD_4
TDI
TDO
TMS
TCK
TRST
REFCLK0
MDC1
MDIO1
MDINT1
MODESEL_0
MODESEL_1
SECTION
AMDIX_EN
MDIX
CFG_1
CFG_2
CFG_3
G_FX/TP
TFIFO
SD_2P5V
R9
4.7K
R611
22
0
R22
4.7K
JP3
HEADER 4X2
12
34
56
78
JP16
HEADER 3X1
1
2
3
D
93
LED RD
R24
4.7K
R17
4.7K
R13
22
0
U2B
74HC14
3
4
S8
SW DIP-6
1
2
3
4
5
6
12
11
10
9
8
7
R19
4.7K
R18
4.7K
R726
4.7K
JP20
R20
4.7K