BenutzerhandbuchInhaltsverzeichnisIntel® IQ80321 I/O Processor Evaluation Platform1Introduction 1131.1 Document Purpose and Scope131.2 Related Documents13Table 1. Intel® 80321 I/O Processor Related Documentation List131.3 Electronic Information14Table 2. Electronic Information 141.4 Component References14Table 3. Component Reference141.5 Terms and Definitions15Table 4. Terms and Definitions151.6 Intel® 80321 I/O Processor16Figure 1. Intel® 80321 I/O Processor Block Diagram161.7 Intel® IQ80321 Evaluation Platform Board Features18Table 5. Summary of Features18Getting Started 2192.1 Kit Content192.2 Hardware Installation192.2.1 First-Time Installation and Test192.2.2 Power and Backplane Requirements192.3 Factory Settings202.4 Development Strategy202.4.1 Supported Tool Buckets202.4.2 Contents of the Flash202.5 Target Monitors212.5.1 Redhat Redboot212.5.2 ARM Firmware Suite222.5.2.1 ARM Angel232.5.2.1.1 Semihosting (File I/O)232.6 Host Communications Examples242.6.1 Serial-UART Communication24Figure 2. Serial-UART Communication242.6.2 Ethernet-Network Communication24Figure 3. Ethernet-Network Communication242.6.3 JTAG Debug Communication25Figure 4. JTAG Debug Communication252.6.4 GNUPro GDB/Insight262.6.4.1 Communicating with Redboot262.6.4.2 Connecting with GDB282.6.5 ARM Extended Debugger29Hardware Reference Section 3313.1 Functional Diagram31Figure 5. Functional Block Diagram313.2 Board Form-Factor/Connectivity32Table 6. Form-Factor/Connectivity Features32Figure 6. Board Form Factor323.3 Power33Table 7. Power Features333.4 Memory Subsystem343.4.1 DDR SDRAM34Table 8. DDR Memory Features34Table 9. Supported DIMM Types343.4.1.1 Battery Backup343.4.2 Flash Memory Requirements35Table 10. Flash Memory Requirements353.5 Intel® 80321 I/O Processor Operation Mode363.6 Interrupt Routing37Figure 7. External Interrupt Routing to Intel® 80321 I/O Processor373.7 Intel® IQ80321 Evaluation Platform Board Peripheral Bus38Figure 8. Intel® IQ80321 Evaluation Platform Board Peripheral Bus Topology38Table 11. Peripheral Bus Features383.7.1 Flash ROM39Table 12. Flash ROM Features39Figure 9. Flash Connection on Peripheral Bus393.7.2 UART40Table 13. UART Features40Figure 10. UART Connection on the Peripheral Bus403.7.3 HEX Display41Table 14. HEX Display on the Peripheral Bus41Figure 11. HEX Display Connection on the Peripheral Bus413.7.4 Rotary Switch42Table 15. Rotary Switch Requirements42Figure 12. Rotary Switch Connection on the Peripheral Bus423.7.5 Battery Status43Table 16. Battery Status Buffer Requirements43Figure 13. Battery Status Buffer on Peripheral Bus433.8 Debug Interface443.8.1 Console Serial Port443.8.2 Ethernet Port443.8.2.1 Intel® 82544EI Gigabit Ethernet Controller443.8.3 JTAG Debug453.8.3.1 JTAG Port45Figure 14. JTAG Port Pin-out453.8.4 Logic-Analyzer Connectors45Table 17. Logic Analyzer Connection453.8.5 Mictor J3F246Table 18. Micor J3F2 Signal/Pins463.8.6 Mictor J2F147Table 19. Micor J2F1 Signal/Pins473.8.7 Mictor J1C148Table 20. Micor J1C1 Signal/Pins483.8.8 Mictor J3C149Table 21. Micor J3C1 Signal/Pins493.8.9 Mictor J2C150Table 22. Micor J2C1 Signal/Pins503.9 Board Reset Scheme51Table 23. Reset Requirements/Schemes51Figure 15. RESET Sources513.10 Switches and Jumpers523.10.1 Switch Summary52Table 24. Switch Summary523.10.2 PCIX Initialization Summary53Figure 16. PCI-X Routing Diagram on Secondary PCI-X Bridge533.10.2.1 User Defined Switches533.10.2.2 PCI-X Bridge Initialization Signals533.10.3 Default Switch Settings - Visual54Table 25. Switch S7E154Table 26. Switch S8E154Table 27. Switch S8E254Table 28. Switch S9E154Table 29. Switch S1D154Table 30. Switch S4D1543.10.4 Jumper Summary55Table 31. Jumper Summary553.10.5 Connector Summary55Table 32. Connector Summary553.10.6 General Purpose Input/Output Header55Table 33. GPIO Header (J3F1) Definition553.10.7 Secondary PCI/PCI-X Operation Settings56Table 34. Secondary PCI/PCI-X Operation Settings563.10.8 Primary PCI/PCI-X Operation Settings56Table 35. Primary PCI/PCI-X Operation Settings563.10.9 Detail Descriptions of Switches/Jumpers573.10.9.1 Switch S7E1- 2/357Table 36. Switch S7E1- 2/3: General Descriptions573.10.9.1.1 S7E1-2: RST_MODE57Table 37. Switch S7E1-2: RST_MODE: Settings and Operation Mode573.10.9.1.2 S7E1-3: RETRY57Table 38. Switch S7E1-3: RETRY: Settings and Operation Mode573.10.9.1.3 Operation Setting Summary Descriptions57Table 39. RST_MODE and RETRY Operation Setting Summary573.10.9.2 Switch S7E1- 4/558Table 40. Switch S7E1 - 4/5: Descriptions583.10.9.2.1 Switch S7E1 - 458Table 41. Switch S7E1 - 4: Settings and Operation Mode583.10.9.2.2 Switch S7E1 - 558Table 42. Switch S7E1 - 5: Settings and Operation Mode583.10.9.3 Switch S7E1- 6/758Table 43. Switch S7E1 - 6/7: Descriptions58Table 44. Switch S7E1 - 6/7: Settings and Operation Mode583.10.9.4 Switch S7E1- 859Table 45. Switch S7E1 - 8: Descriptions59Table 46. Switch S7E1 - 8: Settings and Operation Mode593.10.9.5 Switch S8E1- 260Table 47. Switch S8E1 - 2: Descriptions60Table 48. Switch S8E1 - 2: Settings and Operation Mode603.10.9.6 Switch S8E1- 360Table 49. Switch S8E1 - 3: Descriptions60Table 50. Switch S8E1 - 3: Settings and Operation Mode603.10.9.7 Switch S8E1- 460Table 51. Switch S8E1 - 4: Descriptions60Table 52. Switch S8E1 - 4: Settings and Operation Mode603.10.9.8 Switch S8E1- 5613.10.9.8.1 Switch S8E1 - 5: Descriptions61Table 53. Switch S8E1 - 5: Settings and Operation Mode61Table 54. Switch S8E1 - 5: Driver Mode Output Impedances613.10.9.9 Switch S8E1- 661Table 55. Switch S8E1 - 6: Descriptions61Table 56. Switch S8E1 - 6: Settings and Operation Mode61Table 57. Switch S8E1 - 6: Driver Mode Output Impedances613.10.9.10 Switch S8E1- 762Table 58. Switch S8E1 - 7: Descriptions62Table 59. Switch S8E1 - 7: Settings and Operation Mode623.10.9.11 Switch S8E1- 862Table 60. Switch S8E1 - 8: Descriptions62Table 61. Switch S8E1 - 8: Settings and Operation Mode623.10.9.12 Switch S8E2 - 1/263Table 62. Switch S8E2 - 1/2: Descriptions63Table 63. Switch S8E2 - 1/2: Settings and Operation Mode633.10.9.13 Switch S8E2 - 463Table 64. Switch S8E2 - 4: Descriptions63Table 65. Switch S8E2 - 4: Settings and Operation Mode633.10.9.14 Switch S9E1 - 1:364Table 66. Switch S9E1 - (1:3) Descriptions64Table 67. Switch S9E1 - (1:3) Settings and Operation Mode643.10.9.15 Switch S9E1 - 464Table 68. Switch S9E1 - 4: Descriptions64Table 69. Switch S9E1 - 4: Settings and Operation Mode643.10.9.16 Switch S1D1 - 1/265Table 70. Switch S1D1 - 1/2: Descriptions65Table 71. Switch S1D1 - 1/2: Settings and Operation Mode653.10.9.17 Switch S4D1 - 1/265Table 72. Switch S4D1 - 1/2: Descriptions65Table 73. Switch S4D1 - 1/2: Settings and Operation Mode653.10.9.18 Switch S4D1 - 3/465Table 74. Switch S4D1 - 3/4: Descriptions65Table 75. Switch S4D1 - 3/4: Settings and Operation Mode653.10.9.19 Jumper J1G266Table 76. Jumper J1G2: Descriptions66Table 77. Jumper J1G2: Settings and Operation Mode663.10.9.20 Jumper J3E166Table 78. Jumper J3E1: Descriptions66Table 79. Jumper J3E1: Settings and Operation Mode663.10.9.21 Jumper J3G166Table 80. Jumper J3G1: Descriptions66Table 81. Jumper J3G1: Settings and Operation Mode663.10.9.22 Jumper J9E167Table 82. Jumper J9E1: Descriptions67Table 83. Jumper J9E1: Settings and Operation Mode673.10.9.23 Jumper J9F167Table 84. Jumper J9F1: Descriptions67Table 85. Jumper J9F1: Settings and Operation Mode67External RAID Section 4694.1 Private Device Configuration69Table 86. Private Device Configuration Requirements69Figure 17. IDSEL Routing for Private Device Configuration694.2 Interrupt Routing70Table 87. Interrupt Routing for Secondary PCI-X Private Device70Figure 18. Interrupt Routing for Private Device Configuration70Software Reference 5715.1 DRAM71Table 88. DDR Memory Bias Voltage Minimum/Maximum Values715.2 Components on the Peripheral Bus715.2.1 Flash ROM72Figure 19. Flash Connection to Peripheral Bus725.2.2 UART73Figure 20. UART Connection to Peripheral Bus73Table 89. UART Register Settings735.2.3 Rotary Switch735.2.4 HEX Display74Figure 21. Hex Display Connection to Peripheral Bus74Figure 22. 7-Segment Display Bit Definition74Figure 23. Register Bitmap: 7-Segment Display MSB FE84 0000h (Write Only)74Figure 24. Register Bitmap: 7-Segment Display LSB FE85 0000h (Write Only)755.3 Ethernet765.4 Board Support Package (BSP) Examples775.4.1 Intel® 80321 I/O Processor Memory Map77Figure 25. Intel® 80321 I/O Processor Memory Map775.4.2 Redboot* Intel® IQ80321 Memory Map785.4.3 Redboot Intel® IQ80321 Physical Memory Map - Visual79Figure 26. Redboot Intel® IQ80310 Physical Memory Map795.4.4 Redboot Intel® IQ80321 Virtual Memory Map - Visual80Figure 27. Redboot Intel® IQ80310 Virtual Memory Map805.4.5 Redboot Intel® IQ80321 Files815.4.6 Redboot Intel® IQ80321 DDR Memory Initialization Sequence825.4.7 Redboot Switching83IQ80310 and IQ80321 Comparisons A85Table 90. Intel® IQ80310 and Intel® IQ80321 Evaluation Platform Board Comparisons85Getting Started and Debugger B87B.1 Introduction87B.1.1 Purpose87B.1.2 Necessary Hardware and Software87B.1.3 Related Documents87Table 91. Related Documents87B.1.4 Related Web Sites88B.2 Setup89B.2.1 Hardware Setup89Figure 28. Intel® IQ80321 Hardware Setup Flow Chart89B.2.2 Software Setup90Figure 29. Software Flow Diagram90B.3 New Project Setup91B.3.1 Creating a New Project91B.3.2 Configuration92B.4 Flashing with JTAG93B.4.1 Overview93B.4.2 Using Flash Programmer94B.5 Debugging Out of Flash95B.6 Building an Executable File From Example Code95B.7 Running the Code|Lab Debugger96B.7.1 Launching and Configuring Debugger96B.7.2 Manually Loading and Executing an Application Program97B.7.3 Displaying Source Code97B.7.4 Using Breakpoints98B.7.5 Stepping Through the Code99B.7.6 Setting Code|Lab Debug Options99B.8 Exploring the Code|Lab Debug Windows100B.8.1 Toolbar Icons100B.8.2 Workspace Window100B.8.3 Source Code100B.8.4 Debug and Console Windows100B.8.5 Memory Window100B.8.6 Registers Window101B.8.7 Watch Window101B.8.8 Variables Window101B.9 Debugging Basics102B.9.1 Overview102B.9.2 Hardware and Software Breakpoints102B.9.2.1 Software Breakpoints102B.9.2.2 Hardware Breakpoints102B.9.3 Exceptions/Trapping103Getting Started and Debugger C105C.1 Introduction105C.1.1 Purpose105C.1.2 Necessary Hardware and Software105C.1.3 Related Documents105Table 92. Related Documents105C.1.4 Related Web Sites106C.2 Setup107C.2.1 Hardware Setup107Figure 30. Intel® IQ80321 Hardware Setup Flow Chart107C.2.2 Software Setup108Figure 31. Software Flow Diagram108C.3 New Project Setup109C.3.1 Creating a New Project109C.3.2 Configuration110C.4 Flashing with JTAG111C.4.1 Overview111C.4.2 Using Flash Programmer112C.5 Debugging Out of Flash113C.6 Building an Executable File From Example Code113C.7 Running the Code|Lab Debugger114C.7.1 Launching and Configuring Debugger114C.7.2 Manually Loading and Executing an Application Program114C.7.3 Displaying Source Code115C.7.4 Using Breakpoints115C.7.5 Stepping Through the Code116C.7.6 Setting Code|Lab Debug Options116C.8 Exploring the Code|Lab Debug Windows117C.8.1 Toolbar Icons117C.8.2 Workspace Window117C.8.3 Source Code117C.8.4 4 Debug and Console Windows117C.8.5 Memory Window117C.8.6 Registers Window118C.8.7 Watch Window118C.8.8 Variables Window118C.9 Debugging Basics119C.9.1 Overview119C.9.2 Hardware and Software Breakpoints119C.9.2.1 Software Breakpoints119C.9.2.2 Hardware Breakpoints119C.9.3 C.9.3 Exceptions/Trapping120Größe: 998 KBSeiten: 120Language: EnglishHandbuch öffnen